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I have a chunk of combo logic (synthesizable netlist) where the shortest path is 1 ns and longest path is 7 ns.
My clock is 5 ns but I need single cycle throughput. If I were to pump input every clk and capture 2 cycles later at every cycle, the shortest path will
have a problem, and longest...
I understand there are different bit rates for Wifi.
Maybe I should not have mentioned Wifi as example, rephrase my question.
Assume that I sample a downconverted/bandlimited RF from ADC, and it contains 5MHz, 8MHz, 9MHz.
Are there any digital operation which can convert them into 2.5MHz...
Assume a wifi signal with bw of 20MHz, after RF mixer and LPF, you get an intermediate signal from o to 20MHz..
Is it possible to compress that 20MHz BW signal into a 10MHz BW.. (I dont mean half band filtering with 10MHz)..
And how?
And is it a very stupid question?
Assume the following C code, what's the most efficient method do I use in VHDL, assuming timing is more important than area?
Thank you in advance.
Assume 8 bit Din, 3 bit scl (scaling factor);
K = 7;
Temp = (Din << (K-scl) + (1<< (K-1));
Dout = (Temp >> K) & ((K&0xFF) ? 0xFF, 0xFE);
then keep it for future use, or skip it.. the function is very basic and you will see better implementations than that.
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Another example such function may be useful.
When you receive an QAM (16 and above) modulated signal, the amplitude tend to vary with gain settings...
Not sure where it's used though.. What's the context?
Could be that next stage want to use the full range of a variable.. or is it to maximize the amplitude before going to a transmitter if it were a wireless chip?
Neither can give you a position in today's communication area. It's saturated and only a small number of companies are in.
Being in here for 10+ years and witnessed the number of companies dwindle from tens to a handfull in my country.
By the time you graduate, I guess only a few left arround...
Co channel interference means when two transmitters use the same frequency. It's something you cant prevent.
Adjacent channel interference is when you transmit, your signal spills into adjacent frequency. Normally you are safe if you design with spec, and you can improve by designing a very...
Try look at this, it uses a 64X clock though.
https://ww1.microchip.com/downloads/en/devicedoc/31018a.pdf
Sometimes I am confused with the USART. What does it mean when you will oversample and process the data anyway?
You can insert into both. Consider that your novice answer in the reduce gate count thread is :grin: ask for a training can get you to the advanced level, i.e. where, when and how to insert CG in RTL.
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If the requirement is to add "a clock gate".. then one would guess it's...
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