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LEF:Library Exchange Format
in cadence tools we use LEF
in synopsys tools we use .tf(technology file)
this LEF/.tf contains the info of technology mapped gates with timing,power,area...etc info for each and every cell that is being used in our design
SDC:Standard Desigin Constraints
this is the file generated after synthesis
this file consists of constraints related to AREA,TIMING,POWER(optmization)
max trans,max/min cap. ...etc
LEC:logical equivalance check
lec is one of the formal verification method
lec is performed after synthesis
GDS:GDS II is a database file format which is the de facto industry standard for data exchange of integrated circuit or IC layout artwork
"Graphic Data System"
core utilization is the factor decides the Floorplan
floorplan
1.pad-limited
2.core-limited
in power plan we do
1.by power bumps
2. by power stripes
consider congestion also
consider all these aspects
u need to reduce the core/die area. for better improvement of core utilization
dc_shell
invoke DC from work directory which should contain .dc.setup<file>
maintain directory structure for DC
like
DC is main directory
in this sub-dir
work
source- (.v/.vhd)
ref(libraries)
scripts
netlist
reports
the algorithim used by prime time for timing analysis give optimised results compared to soc encounter
this is the job of EDA tool developer to design algorithim for timing analysis
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