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Thank you all for your comments.
As for the case comments, I have tried to simplify the original code as much as I could to highlight my real problem, that meant removing states. I left the default state for the B state as a safe mechamisn, that is, to be sure stateReg doesn't contain anything...
Hello,
Thank you for your answers! Akanimo, I think your code doesn't implement what I am trying to achieve.
I have simulated the last code I submitted and it seems to work, my concern is if there is a better way to do this or not. In particular this process:
process(clk)
begin
if...
Thank you all very much! I see my view of VHDL is not right...
My intention is to register "input" pin in the rising edge of the clock and at the same time output '0' through "data". In the next rising edge I want to output the value of "input" in the previous cycle and repeat again and again...
Thank you very much TrickyDicky!
The code is as follows:
library ieee;
use ieee.std_logic_1164.all;
entity Test1 is
port(
rst, clk, input: in std_logic;
data: out std_logic
);
end Test1;
architecture rtl of Test1 is
type state is (A, B);
signal stateReg, stateNext: state;
signal...
Hello all!, I am learning VHDL, sorry if this is too obvious or doesn't make sense at all.
I am trying to implement a FSM whose inputs are only registered synchronously, that is, the output logic process only contains CurrentState in the sensitivity list and it is updated on the rising edge of...
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