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hello everyone >.....
I desired to study DSP,Imaging Processing...and all about Imaging processing so long ..... but I don't have enough time to do that.... ,this summer , i quite have enough time to study VHDL, Verilog , ASIC, and DSP...... but the difficuties to me that I don't know what...
Oh thank for all ur help...........
I have the first book of Smith.... but the "Advanced ASIC Chip Synthesis" by Himanshu Bhatnagar I don't have can anyone show me a link to it....
best thanks
hello everyone
I got the problem with the odd number of Clock to generate baudrate . I want to generate baudrate at 2400,9600,115200....and more ...
can u help me
best regard !
depend on who works for what project !
By myself .... I think @ltera Baseline 10.2 and Altera Advanced Synthesis is very good for whom is the first user......
Oh ..... i don't think so
.....
In a positive sense ... I think VHDL is very interesting language to learn .....
When u have a sense of it u will know how interesting it is........
Oh.....
I do this job just to simulate for acknowledge >..... but with altera I can't do any simulation because they don't support acess type so we can't use the pointers.....
.....
Oh thank for all ur help .....
but a new problem occurs that MaxPlus doesn't support for access type that the most important tool for access line string so.........
There is a problem like this .....
I must build in block that can recieve continuous 8 serial bits and then change into a byte then transfer it to a control block to process ... the problem that how can i detect the start bit and the stop bit when i continuouly receive the bit streams.......
Re: design fifo
what the concrete project do u want .
I have VHDL code for fifo . I hope it can help u !
-- A First-in First-out Memory
-- a first-in first out memory, uses a synchronising clock
-- generics allow fifos of different sizes to be instantiated
-- download from: www.fpga.com.cn &...
what should u want to do ?
why there are so much digits on one pin
to do that u should define a vector and use test_vectors to test it function...
let try.
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