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library ieee;
use ieee.std_logic_1164.all;
entity adder is
port(a:in std_logic_vector(3 downto 0);
sum:out std_logic;carry:out std_logic);
end adder;
architecture behaviour of adder is
signal c0,s0:std_logic:='0';
begin
s0<=a(0) xor a(1) xor a(2);
c0<=(a(0) and a(1)) or (a(1) and a(2))or( a(2)...
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