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Hi,
I know the difference of average and peak power, however the total power is different between these two analysis of my design (using the same testbench-full annotation). Does this make sense? If yes, why? If not, where should I place my effort to debug this issue?
my best,
Harry
After some working around that I noticed the followings.
The lib.v, which contains all the functional verilog modules for all cells in the library, I had included it at my top.v file (post-routed netlist) in order to find the cells modules. Therefore when I run ncverilog command this creates...
Hi,
I manage to run gate-level simulation of my post-routed netlist with ncverilog, and i can observe the increased delay of all cells and nets at simvision. My only question is about the sdf statistics that ncverilog reports, as I would excepted 100% annotation but it reports only 2.67% for...
Hi,
As the title of this topic indicates, I want to synthesise and P&R a design without buffers in order to observe the behaviour of long interconnects to the delay. Therefore, I want to know if there is any way to disable buffer insertion to my design, both at the stage of synthesis (Design...
Hi,
I have the resulting netlist of small design (either from Synopsys or Encounter, doesn't matter) and i want to create a hypergraph file of this netlist. Basically i want to put the hypergraph file as an input (.hgr file) to hmetis partitioning algorithm. Therefore my question is: Are these...
Hi guys,
I recently downloaded some technology libs and they have an hspice folder with a .spf file inside with the gates as .SUBCKT. So my questions are:
1. In a .sp file i can include this .spf file and use the .SUBCKT as elements in my design and run simulations in Hspice. Am i right?
2...
Hi guys!
I am new here and i would like to ask how can I create blackboxes (or Hard macrocells??) in Synthesis and PnR stages. I am only asking for general guidelines as i don't want to make things much complicated for you.
So for example I have an RTL code and i want to synthesize (Design...
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