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Recent content by kaiserschmarren87

  1. K

    Soft ECC or Built-In ECC for Single Port RAM & True Dual Port RAM?

    I have to implement Hamming Code ECC to Single Port RAM and True Dual Port RAM. At the moment 32/64/128 bit HC ECC has been implemented but takes more resources. I know that there is Built-In ECC and Soft ECC for Simple Dual Port RAM and I do not see for Single Port RAM and True Dual Port RAM in...
  2. K

    [SOLVED] CRC for SENT Protocol

    This should help you: http://electronics.stackexchange.com/questions/92529/implementing-parallel-crc-in-verilog Or else try to generate using online tools: http://outputlogic.com/?page_id=321 http://leventozturk.com/engineering/crc/
  3. K

    have Multiplier code but i am getting error stating - near "end" : expecting identier

    Re: have Multiplier code but i am getting error stating - near "end" : expecting iden I guess you missed a bracket for the entity - port section: entity Array_Multiplier is Port (A,B : in bit_vector(3 downto 0); P: out bit_vector(7 downto 0); Result_Low : out...
  4. K

    how can execute process for one time synthesizable?

    You can use a process which is synthesizable. You can write a state machine or define a mux or any logic to be implemented with a sensitivity list either clocked or combinational one. Taken from Duolos: A process is a concurrent statement inside an architecture body just like a component...
  5. K

    how can i use another multiply algorithm in my code?

    Where is the code? That would help!
  6. K

    CRC Generator - This circuit and VHDL? (I need only explanation)

    Thank you for the explanation vGoodTimes :) I have another question regarding CRC Generator and Detector. I got this Parallel CRC calculation document: https://apt.cs.manchester.ac.uk/ftp/pub/amulet/papers/MGrymel_TVLSI10.pdf It says, suppose I use the below parallel CRC calculation VHDL code...
  7. K

    CRC Generator - This circuit and VHDL? (I need only explanation)

    Hi, I have understood what CRC algorithm is. I found enough information online. Also found online tools to generate VHDL code for the specified data and polynomial. Could someone be generous to explain how the data and crc bits are chosen for CRC generation in this VHDL code generated from this...
  8. K

    lcd interfacing in spartan 3E using vhdl

    I read all the previous replies and tried myself to put the code in this order. I wrote an FSM for the code with a counter to keep track of the counting. The counter value is not specific here and I have used a sample. I have not completed it but thought this could be a solution. I hope it is...
  9. K

    calculator disign using key encoder

    There is a thread with some information about the calculator program here: https://www.edaboard.com/threads/160846/ It would have been better if you could share the code to analyze.
  10. K

    Gray counter code error

    TrickyDicky is correct. I will just post an answer which I got from Xilinx forum: "Since these warnings appear at time 0, they probably happen because not all signals have been assigned a useful default value ('0' or '1'). Without that these signals carry 'U', such causing the warning. Make...
  11. K

    Gray counter code error

    Just make this change: GrayCount_out <= (BinaryCount(COUNTER_WIDTH-1) & (BinaryCount(COUNTER_WIDTH-2 downto 0) xor BinaryCount(COUNTER_WIDTH-1 downto 1)));
  12. K

    Zynq zc702(Creating a First IP Integrator Design) using Xilinx 14.3 Planahead???

    Zynq zc702(Creating a First IP Integrator Design) PS part not clear.. QUESTION Regarding PS Part: Hello, I am new to Zynq(PS+PL) system and Vivado tool. In my project I have to use Xilinx ISE 14.3 with Zynq zc702 evaluation board. I have to work on using PlanAhead and XPS for this. I am...
  13. K

    Formal port/generic <> is not declared in--- ERROR!

    Formal port/generic &lt;&gt; is not declared in--- ERROR! Hello, In the design which I am working on, I need to pass a std_logic_vector(15 downto 0) from a register in the top module to an input port of a sub module. I have done it in the following way: -----top_module---- signal...
  14. K

    Getting either integer or std_logic_vector value to generic. (Or any alternatives)

    Hallo, I have to pass a (6 downto 0) value (it is an output as std_logic_vector) from my top module to one of the sub module(as Generic). Is there any work around for this? (I know that an integer value contained in a signal can't be mapped to a generic variable. To explain it clearly: Top...
  15. K

    Error: Unable to to read LMC Smartmodel library file !

    Hello all, I am simulating my design from Mentor Graphics HDL Designer and trying to check it in ModelSim. Earlier it used to work fine but these days it is showing this error: **Error: Unable to read LMC Smartmodel library file. Can somebody please explain the solution for this ? Should I...
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