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Look at the **broken link removed**
SPI runs at 3.6 MHz max (at 5V supply) and ten bits are transferred per sample.
This gives a conservative 200,000, ten-bit samples per second
Re: devce deaign using polling for switch scann seems useless "waching machine
The replies to this thread (except this one) are the best advice the OP will ever receive on the subject.
I think post #4 had your answer, or at least outlined the questions you need answered.
You or somebody else must decide on a clock frequency, its resolution and jitter.
Then match these numbers in your simulator.
Also: it's not an 'irrational' period; it's a repeating fraction
Re: How to design DC-DC to let output voltage follow input voltage?
This requires a more complete specification.
Voltages available, frequency response, power-handling needs...
Also: the latest version of Quartus that supports Cyclone II is 13.0, released a few years ago.
Don't let that deter you, though: those ebay Cyclone boards are useful and I've had a lot of fun with them
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