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Re: Help:synchronous of data and clock in mixed signal syste
Thanks for your reply:
When the analog designer giving the synchronous data and clock, Can the digital designer using the same clock and data?
I means in our systems, we use pll for clock synthesizer, and the PLL gives the clock...
In mixed signal systems, how to ensure the syncrhonous in exchanging data in the interface of Digital and Analog? e.g. the output data of ADC shoud be sent to digital, then I should send a synchronous clock, But how should I ensure it?Here the main concern is clock skew issue.
clock tree? but...
Re: help: What should I do before block test in analog tape
Thanks.
And do you have characterization report model for analog IC test ?
or could you give me a link about this report model?
Re: help: What should I do before block test in analog tape
Thanks for all your reply.
I mean the test chip has arrived back. I will test it next few days.
Can I connect the supply to the chip without any extra test?
The DAC is hybrid converters, high MSBs using thermometer, while LSBs using binary code. I have given it enough time to settling down. And I have observed the vdd variation, it will settle in several nano second, and the digital code is about several kilo herz. it is a ideal inductor. In our...
how to simulate a inductor in hspice
I have added a 10n inductor in series with vdd to simulate the actual situation(is it right?). But I now found the circuit(it is a low speed DAC, the DAC has no latch, i.e. no clock) work weirdly. when I give the digital from all 0 to all 1, it is not...
Thanks for all!
Because we don't know the real die size and we maybe take a long time to design the ADC, we change the system. And we don't use ADC now.
When I make post-simulation, I want to give the supply a reasonable model. I know there are bonding and leading para. cap and inductor? which value is appropriate? thanks
I want to design 60MSPS 6bit ADC, and the die size is in the concern. which architecture is sutiable, and could you tell me the approximate die size in 0.25um process? Maybe the flash's size is too huge in 6 bit , I think.
To wylee:
For some simple circuit, It may be correct. But for some complicated circuit, we should consider the operating point and slew rate and maybe other things.
To papyaki ,riz_aj
I use hspice as my tool, and I don't know about pspice.
And generally what isthe cutoff frequency? 10%...
To wylee:
For some simple circuit, It may be correct. But for some complicated circuit, we should consider the operating point and slew rate and maybe other things.
To papyaki ,riz_aj
I use hspice as my tool, and I don't know about pspice.
And generally what isthe cutoff frequency? 10%...
I want to simulate an LPF's BW. I have heard AC simulation is not precise. So I use TRAN analysis as follows: I give a low frequency signal to the input, and measure the output signal Vout0, and take the Vout_3=Vout0 x 0.707 as the -3dB frequency. Is this resonable?
And are there any other methods?
cadence edif import
I design a mixed circuit, and I want to simulate it through s*nopsys design analyzer and cadence. I design digital part in verilog, and then synthesize it in DA, and save it as edif file. When I want to import it into cadence, I failed. I in fact want to simulate in...
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