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Recent content by juliog

  1. J

    Design Compiler and Gate Strength

    Hello guys, Is it possible to tell design compiler that is it only allowed to change gate strengths during a compilation? E.g., changing AN2S gate por AN2T gate. Obviously, the input would be a circuit (netlist) already mapped into a technological library. In other words, after a first...
  2. J

    Design Compiler Operating Conditions (Warning)

    Hi, @bigdogguru: I'm using version 2007.03-SP5 @paulki: The version of DC I'm using doesn't have a '-typ' option for this command (the command you wrote results in error). I don't think I'm targetting typical corner, I'm trying to specify extreme conditions (min_max mode). It seems strange...
  3. J

    Design Compiler Operating Conditions (Warning)

    Hello guys, I'm getting the following warning when compiling a design: Warning: Operating condition WCCOM set on design c432 has different process, voltage and temperatures parameters than the parameters at which target library fsa0a_c_sc_tc is characterized. Delays may be inaccurate as a...
  4. J

    Four-Terminal sensing

    Thanks, really helpful.
  5. J

    Four-Terminal sensing

    Thanks for ur help. As the system is driven by a current source, the voltage amplitude across Rx is always the same, isn't it? But the votage amplitude at input (Rx+2Zp) increases with lower frequencys. So i think you mean higher frequencies are "safer" to avoid an overdrive, right? The first...
  6. J

    Four-Terminal sensing

    Yes, but the voltage amplitude is the same for all frequencies... isn't it? Four-terminal sensing - Wikipedia, the free encyclopedia We just want to measure Rx (R in the wiipedia circuitry), Zp would be Rl
  7. J

    Four-Terminal sensing

    Hi guys, I was having a look at these questions about a four-wire measurement system and I'm not sure about the answers: A four wire system is employed to measure a resistive load, Rx. The model for each electrode Zp is the parallel combination of a resistor Rp=1MΩ and a capacitor Cp=1nF. The...
  8. J

    Power amplifiers and inductors

    Thanks for ur answers... really helpful!
  9. J

    Power amplifiers and inductors

    Thanks again... But wouldn't be a better approach to use active loads for small signal?
  10. J

    Power amplifiers and inductors

    And why can we tolerate a DC voltage drop in the case of a small signal amplifier but not for power amplifiers? And even if we can tolerate it for small signal, why not to use the inductor anyway? Thanks for ur help!
  11. J

    Power amplifiers and inductors

    Hi guys, I know it's a very elemental question, but I was having a look at several book and I couldn't find a clear explanation :( Why is it normal to place an inductor between NMOS drain and power supply in a power amplifier? I know it's a choke inductor... but I cannot see the point. Why is...
  12. J

    Fully differential OPAMP slew rate simulation and monte carlo analysis

    Hello guys, How can I cancel the offset produced by transistor mismatches (monte carlo analysis) to measure the slew rate (trans analysis)? I want the offset to be cancelled for each iteration of the monte carlo analysis, but of course i cannot calculate the input-referred offset... it's...

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