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Recent content by jrwebsterco

  1. J

    What is a 'unexpandable_clocks' in PrimeTime's check_timing report?

    Are you already familiar with how PT will "expand" the periods of two clocks with different periods in order to find e.g. the least-common-multiple time where both clocks have a coincident edge? (e.g. the effective period gets expended in the timing-report in order to find the tightest slack...
  2. J

    Library preparation for Design Compiler in topo mode

    Your assumption is incorrect. First, make sure you selected "Topo" or "DCT flow" or something like that as an option to the RM-script downloader on SolvNet. (I don't recall if Topo flow is in the default config for the RM script for DC) Second, look at file rm_setup/dc_setup.tcl, and search for...
  3. J

    SDF error (encounter to primetime)

    The only idea would be that there is a structural mismatch between the SDF and the netlist you had read-into PT. The message indicates that the netlist does not have a direct connection between the two cell-pins it mentions. Have you tried to ... -> Pull the netlist into an editor ... -> Pull...
  4. J

    VCS mixed mode compilation - no optimization

    Chapter 10 of the User Guide titled Gate-level Simulation should adequately explain the usage of the -sdf elaboration command-line option for you.
  5. J

    Question on WLM and DC topographical mode

    I assume you mean "auto place&route" by APR? (just use P&R - it is more conventional) You apparently are wanting to avoid needing to use DC-Topo. Do you actually have real WLM's available in the std-cell library you plan to use? (most libs at 180nm and smaller no longer provide WLMs, and you...
  6. J

    How to Resolve this for loop error..

    I'd suggest your problem is using the "assign" keyword inside of a behavioral block ("always @" in this case). Only use "assign" for a continuous assignment outside of such behavioral areas. You should simply delete the "assign" statement for "temp" inside that always area. (Note it is correct...
  7. J

    How to make a long- lasting led light powered by button cells.

    FWIW, the LM3909 LED Flasher/Oscillator IC was intended to maximize LED duration from a 1.5V cell (now old but maybe still available out there). One of the app-circuits was for a booster (not a flasher) that drew only 4mA while feeding the LED with short high-current pulses @ 2kHz (constant to...
  8. J

    Improvised Guitar Pickups

    I agree - it appears you are effectively using microphones as an electric guitar pickup. The reason is likely because the coils can be moved by the acoustic vibrations from the amplified speakers, in addition to having induced currents due to the moving strings. You really only want the latter...
  9. J

    Verilog - Files management

    And ... that spec is currently free at: Grab it while it still is!
  10. J

    Implementing FPU on FPGA using Verilog

    I'm afraid don't have the time to go and chase down references you seek - I do not have any already on hand and you can easily search for them yourself. I think that you are getting into usage and flow and handshaking details, which is something you would need to think through as part of your...
  11. J

    [SOLVED] verilog syntax question

    It's an *optional* identifier (i.e. a label or name). You only need it if you wish to reference it from a disable statement or to hierarchically reference local variables declared inside that sequential-block hierarchy. (some simulators might also use it for more verbose log/debug messages if it...
  12. J

    Implementing FPU on FPGA using Verilog

    In fact you could perform an addition in *one* cycle using only combinatorial logic, but the propagation delay would require a low frequency for each new operation, and might not be usable for most S/W applications. Note that the configurable Xilinx CORE Generator IEEE 754 function will let you...
  13. J

    [SOLVED] Signal Count cannot be synthesized

    You've got a few problems here. One is that you are not using the correct expected "template" structure for describing reset as either an async or sync reset. (if sync-reset then the conditional if's need to be inside of the edge-clocked area, but if async-reset then reset is missing from the...
  14. J

    Implementing FPU on FPGA using Verilog

    Not knowing what the actual goal is of your project, I'm not sure what to comment on about a paper. What are you trying to do that has not been done and documented before? Or is it intended to be of a tutorial nature? (for IEEE 754 concepts, or for FPGA implementation concepts, or for...
  15. J

    Implementing FPU on FPGA using Verilog

    Yes it is possible. It seems you have multiple options ... -> Take a look here: https://opencores.org/projects You will find multiple FPU designs and also dedicated FP arithmetic blocks that all support IEEE754. -> Use the Xilinx CORE Generator (which is part of the ISE install) to generate...
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