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vdsat negatif
As Vgs-Vt approaches zero, the device is no longer working in strong inversion, and a different set of rules occurs because the conduction is no longer dominated by drift. Using vdsat = vgs-vt is only valid in the strong inversion region.
The device goes thru a transition region...
It is difficult to tell from your description, but I would guess that there is a load influence on the comparator, or more specifically an influence of mismatch of the load. This can be often found in a latch type comparator. If your comparator is this sensitive to mismatch in load, it must be...
constant gm bias
A- This is the typical "constant Gm" bias generator. This circuit works pretty good, and produces an easily derived current level. In order to produce a significant voltage on the resistor, the current densities in the two NMOS are typically VERY different (either by having...
My guess is that you are running into problems with M3 & M4 going into linear region rather than saturation, starving the current out of the folded stage. You can check this by verifying the current levels in each leg of the amplifier.
There are a couple of things you could do to prevent this...
Re: about comparator design
It sounds like you are using the comparator in an "auto-zero" type configuration. That changes everything, since in the autozero phase, it is essentially an amplifier in unity gain feedback.
What I would suggest in order to maintain auto-zero capability is to...
Are there any other specifications?
Input impedance?
How fast does the comparator need to transition?
What temperature range does the comparator need to operate over?
What is the tolerance on the 150mV?
What other circuits might be available? Reference voltages? Bias currents? Clock...
comparator bode plot
The compensation of an amplifier is needed for it to operate in a negative feedback orientation. Phase margin is really only a measure of stability when an amplifier is used in a unity gain configuration using negative feedback. Feedback is used to provide a specific gain...
inside the op-amp and negative feedback
I would say that the primary purpose for a differential first stage in an op-amp is to allow a wide input voltage range (common mode range of opamp). Most single ended amplifier stages have quite a small range of useful input voltage.
bjt bandgap reference
There are many, many trade-offs for the current in the bandgap components.
POWER - Of course the most direct item impacted is power consumption.
AREA - In order to achieve lower current (power), you need bigger resistors.
ERROR TERMS - If you bias at too high of a...
taik,
There are a few things that can be done to improve the matching.
The first is to increase the size (area) of the transistors.
The second is to bias the transistor out of weak inversion. If you make the transistor a long channel length with a small channel width, it can push the...
taik:
It sounds like what you are saying is that the transconductance per current ratio is high for a MOS in weak inversion. If that is what you are saying, you are correct.
The transconductance (gm) of a MOS in weak inversion can be coarsely calculated as gm = Id/(n*Ut). n is typically...
This depends upon your requirements, as there are trade-offs.
The PMOS almost definitely should be in strong inversion for best matching of current levels and reduced noise contribution. Using a long channel PMOS is good here, as it will push the device farther into strong inversion, improve...
It sounds like settling time is not the issue.
Next thing that comes to mind: Is the preamplifier always in the same state at the sampling time? It could be that the preamplifier goes from being saturated in one direction to saturated in the other direction when the sampling switches are...
One way to test for insufficient settling time in the DAC would be to run the ADC with a slower clock. If the problem decreases or is eliminated, then a settling time issue is most likely the cause.
sar code switching dnl
It looks to me like the ADC has some "memory" of a previous compare. Some suggestions to look for:
Insufficient settling time on the DAC. This would likely worst on the MSB transition, as you are seeing. If the DAC has not settled to 16bits (>11 time constant...
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