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Re: high resolution (15 bit) delta sigma ADC simulation prob
The difference in SNR actually depends on the order of my DSADC. For 3rd order, the difference is about 5dB (I suspect if I get more data points, I can have the 2 match). But for 5th order, the difference is much more (>10dB) , and...
cadence sigma delta reltol
I am designing a rather high resolution (>15bit) delta sigma ADC. I have a design that's working in MATLAB and I am trying to build the same thing in cadence using Verilog A modeling. Every component I have now is ideal and in verilog A code, so that means no...
Hi, i m designing a CT delta sigma ADC. I was wondering about the following,
1. Without using an on chip PLL, what is a realistic clock jitter that my ADC has to be able to tolerate?
2. How do I simulate clk jitter in simulink
Thanks
I have a q about the equivalence between DT and CT DSADC. I know in MATLAB, there is a function u can find H(s) from H(z) if and only if u use NRZ DAC. I am wondering how I can find H(s) from H(z) if I use some other DAC like RZ, exponential, etc...
Thanks
matlab delta sigma
I have a confusion involves the SNR comparison of DSM simulated in MATLAB and VA. In MATLAB, I can get the theoretical maximum SNR (88dB) using transfer function blocks and quantizer block. But in VA, it gave me 68dB (I used the laplace transfer function in VA to create my...
Ya, so I switched out my ideal switches to real MOS switches but i m getting some really weird things....first there are spikes when it's not supposed to be....I swear they are NOT charge injection coz they are happening when the clk isn't switching.... and they are at much higher frequency than...
My DSM is continuous time, so since there is no switched capacitor, i dont think there will be conservation of charge problem.....
So did ur problem go away once u put real switch in replace of the ideal ones?
Thanks
charge injection simulation spectre
I am running into a problem when I was trying to simulate my DSADC in spectre. The entire system is using ideal components (no transistors, but there are VCVS, R, C) and Verilog models. When I was doing transient sim using "Liberal" setting, for about 60us...
I am running into a problem when I was trying to simulate my DSADC in spectre. The entire system is using ideal components (no transistors, but there are VCVS, R, C) and Verilog models. When I was doing transient sim using "Liberal" setting, for about 60us, it was running fine and giving correct...
zero diagonal found in jacobian
I am running into a problem when I was trying to simulate my DSADC in spectre. The entire system is using ideal components (no transistors, but there are VCVS, R, C) and Verilog models. When I was doing transient sim using "Liberal" setting, for about 60us, it...
Hi, I was wondering....to simulate DSADC in transistor level, is long transient + taking the power spectrum the only way to simulate the design? Because this can sometimes take weeks.....is there a faster way?
Thanks
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