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Recent content by johnz

  1. J

    How to deal with memory in a processor?

    In general project, you can use memory compiler to generate memory, But, for a processor, should use full_custom design to implement high-density and high speed, low power.
  2. J

    FE and FB view in physical design

    backend view include lef, milkway, spice, cdl file for lvs, sometimes even has gds file. eda tools cannot do physical design without backend view.
  3. J

    Help me read this timing analysis

    Re: timing analysis This is a cell delay. cell reference name is "AOI21X1" cell instance name is "DTMF_INST/ULAW_LIN_CONV_INST/i_150" Delay type is absolute, not incremental. The max 0->1 delay from A0 pin to Y pin is 0.3143 The typical 0->1 delay from A0 pin to Y pin is 0.3143 The min 0->1...
  4. J

    How to call C tasks in Verilog source codes?

    can take look this book: The Verilog PLI Handbook : A User's Guide and Comprehensive Reference on the Verilog Programming Language Interface there are some example in this website: **broken link removed**
  5. J

    SDF file and slk file

    use less in linux or unix. less is faster than vi when open big file.
  6. J

    set_clock_uncertainty does not affect IO timing analysis

    io timing analysis you must take account clock insertion delay for analysis of IO timing. to over-constrain boundary logic, margin should be added to input delay and output delay, clock uncertainty don't represent margin.
  7. J

    Detailed info about set up & hold

    Re: set up & hold I think best one is Prime Time user guide.
  8. J

    How do I get more hold time slacks after PAR with Astro.

    Hi wkong_zhu, I can try PC and PKS to do post-routing optimization, using best case library , setting minimium wire length and slack criteria.
  9. J

    Does Cadence PKS is a good software?

    I have used PKS for one year and employ it to place, it is not bad. But more people use PC. I don't compare them. placement of SOC encounter is more powerful, PKS documents cadence release are less then before.
  10. J

    Tools for Static Timing Analysis

    both Prime time and Celtic have Static Timing Analysis engine. For now, Prime time is more popular. But below 0.13 um, analysis of cross-talk is very important, Celtic is good at that.
  11. J

    Error when running testbench file by ModelSim

    Re: How can I solve this? Hi laglead, I just want to try another coding, you can thynthesize it by yourself, take look whether their results are same.
  12. J

    how to place & route in CADENCE?

    can take look some tutorials in soc encounter direction like that encounter_installation_direction/etc/share/~ .
  13. J

    Error when running testbench file by ModelSim

    Re: How can I solve this? maybe can try this: always @(posedge clk) if(wb_cyc_i) cyc_cnt <= cyc_cnt + 1;
  14. J

    how to merge multiple SDC

    Hi , recently, I do physical synthesis. there are five sdc files for two functional modes and three test modes. I want to get a mixed and closer sdc used by physical syntesis tool , such as smallest clock period, common false paths and multiple cycle path. It is said that SOC...
  15. J

    assign statement in netlist

    Hi, two reasons cause assign statement in netlist. 1. two or more poort connected to same net. 2 . a port directly connected to 1'b0 or 1'b1 you can try: for PKS 5.2 : set_global multiport_fix_buffer_const_nets true foreach module [ find -modules -hierarchical ] {...
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