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cml output
Our design has the CML output buffer, before it is the amplifier stage. In design, we considered teh mismatch of the amp satge and CML stage and found no issues on the duty cycles for the output eye-diagram even with the output offset up to 200mV. But for the silicon test, we found...
hi, deal above all,
Pls. see the attached files. This is the datasheet of a quad LVDS transmitter from National Semiconductor. It ha the failsafe function at in floating inputs. I guess, when the input pin is in float status, it acts like as an antenna, it will trigger the LVDS transmitters to...
esd diode to vss
We know there have two diodes which are conneced to VDD and VSS respectively to clamp the positive and negative pulse for the protected pin. But I noticed some pins in some cicruit has only one diode connectd to VSS. Anyone help to explain to me? In what conditions, only one...
What is undershoot? Is it the negative of overshoot? Or is it means the rising and/or falling edges do not reach high or low level within the first half of the
unit interval? Or both these two cases can be called undershoot?
Thanks
national cs080
hi,
Many lvds interface circuit from National semiconductor is fabricated with cs080 cmos rpcess?
Anyone can tell me what about this process? It is equalent to 0.6um, 0.5um or 0.35um,etc..? Any special features about this process?
Thanks in advance
Hi, omsi
thanks for the reply!
I replaced the p+resistor with an ideal resistor and redo the simulation, but found the bandwidth has no any descrepancy. The p+resistor is the load of the diff pair. As my understanding, the parasitic pn capacitance should affect the bandwidth if it is inclueded...
Hi,
We used the p+ resistor in our design. We know there are some parasitic reversed pn junction capacitance for p+resistor. I want to know is it this parasitcic junction capacitance has been included in the spice model? i.e., the pre-layout design has considered this effect when spice...
Hi,
I always see the "Electrical characteristics" which includes the dc and ac specifications in the commercial IC product. In the specifications, it always gives its minimum, typical and maximum spec, I want to know how to define this min and max, i.e., its worst case and best case? Is it...
dc offset correction
Hi,
I have aquestion on the dc offset loop for a high gain amplifier, e.g., a limiting amplifier.
We know in the high gain amplifier design, we always need a dc offset loop to reduce the mismatch effect. It consists of a low pass filter which is to extract the dc level...
hysterisis comparator
hi,
We desiged a hysterisis comparator with 0.25um TSMC process. The target hysterisis of comparayor is 17mV.The circuit utilized is the well known topology as attached. The silicon test results on hysterisis is as below:
********
VTRP+ VTRP-
sample 1...
hspice monte carlo
Hi,
I am doing the Monte carlo analysis for my comparator circuiut. To get the more accurate statistical charercter, I run 1200 times for Monte Carlo analysis. But after running some time, I found the CPU become slower and slower. After checking, I found the hpice generate a...
Many papers assert that the PECL output driver is difficult to implement with cmos.It seemed that only IBM has a patent about the PECL driver with cmos.
Would any one tell mehwy it is difficult to implement it with cmos?
Thanks in advance
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