Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.
I suppose you meant: if the bias (colector or drain current) decreases, the gain falls.
However it implies lower linearity of the amplifier (output IP3) and that's not like to broadband signals (like several 8 MHz multiplex of DVB-T).
Hello all. Does anybody know how to design the typical VGA for a commercial TV preamplifier?
In the picture attached, i dont know if the trimmer (7 to 22 dB) is a variable resistor or a variable capacitor. How does it work?
Thank you.
Hi all. I have implemented on PCB the circuit attached (LNA with bypass) but it's not working properly.
If I open the circuit at node VA, and apply an external voltage of 5V, as a control analog signal of the switch, the bypass is done by the two switches (SW1 and SW2), each one is in the state...
How to calculate noise figure for frequency F1 in the following system?
RXin@F1 -> LNA -> MIXER1 -> AMP@F2 -> MIXER2 -> DRIVER -> TXout@F1
F1 es the same frequency for RXin and TXout.
Mixer1 downconverts F1 to F2 (intermediate frequency), and Mixer2 upconverts F2 to F1, where F2<<F1
How is...
Hello all,
in a FM modulator with PLL, I wonder if someone knows the ratio which is usually used between the PFD (phase frequency detector) and the DC modulating frequency. I think PFD must be greater than the DC modulating frequency, otherwise PLL will not work. Is that true? Does anyone know...
Your LNA has a large bandwidth. Have you checked that the input and output matching (S11 and S22) are 50 ohms all over the band? In other words, your -20dBm P1dBin is always the same for all the bandwidth? Good matching mus be done with inductors and capacitors, and the gain can be increased...
markdem,
Of course I should put the ADC as near as possible to the analog circuit that will be converted into digital. Thus, it doesn't mind if digital traces of the ADC are too long till reach the digital board.
Regards
Yakex,
The main noise is due to spurious, phase noise (jitter) and harmonics all generated by a DDS or PLL.
Moreover, for filtering the power supply you can place a typical PI-filter with capacitors and a choke, or even a linear regulator could be placed if your original power supply comes from...
I think you cannot compress the fluctuation. Furthermore, the datasheet is giving you the dynamic range at +/- 1dB error. What's the resolution of your ADC (milivolts per bit)?
Maybe you can represent the symbols with both possitive amplitude and phase, instead of real and imaginary parts which can be either possitive or negative.
Type in google 802.16 and you'll find some document explaining how the number of subcarriers must be selected, depending on your channel bandwidth and FFT points.
This site uses cookies to help personalise content, tailor your experience and to keep you logged in if you register.
By continuing to use this site, you are consenting to our use of cookies.
