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Recent content by jjean

  1. J

    Creating VCD using the lsi_dumpports command questions

    lsi_dumpports Hello everyone, I was trying to dump a VCD for a design using the lsi_dumpports command. I needed to dump out the ports in the design as well as enables for bidirectional ports. The enable signals would be nets in submodules of the design. How do I use lsi_dumpports to create a...
  2. J

    Setup/Hold time violation -- Frequency dependancy

    setup hold time Suppose you have a register to register path with each register clocked by a clock of frequency 10 MHz.Consider a clock edge at time 0 at reg1 and a clock edge at time 0.1us at reg2.The setup check would be between these two edges.But if the frequency varies the time available...
  3. J

    Query regarding timing from faster to slower clock domain

    Re: Query regarding timing from faster to slower clock domai Hi Gavinsun, You're right. 4 and 4 is more constraining. Thanks, Jean
  4. J

    Query regarding timing from faster to slower clock domain

    Hi all, I had a question regarding timing from a faster clock domain to a slower clock domain, say clkA to clkB. Consider the launching clock to be of period 2 (0,1) and the capturing clock to be of period 4 (0,2). So, the base period is 4. The most constraining setup check is between launch...
  5. J

    Query concerning multicycle paths

    I have a question regarding multicycle paths.Consider the following scenario. There is a combo path between two flops clocked by the same clock.The combo path takes more than 5 clock cycles.To handle this properly, 1)In the design ,we introduce a shift register so that the capturing flop is...
  6. J

    Timing optimization of scan paths

    Thanks a lot...
  7. J

    User defined test point for memories while Scan Insertion

    Hi, I was doing scan insertion for a design which has a few memories.Since I saw that the inputs and outputs of the memories could not be fault detected, I added user defined test points for the i/o of the memories.But I see that the coverage has not increase and Tetramax still shows these...
  8. J

    Timing optimization of scan paths

    Do you mean that since there is no combo logic between the scan flops in scan mode,setup violations will not occur and so,even if the scan paths are not constrained,timing would not be a issue? But hold violations can occur in the scan path and they have to be taken care of,right? Also if the...
  9. J

    Timing optimization of scan paths

    Hi, I have a question regarding scan insertion. How is timing for scan paths taken care of?While doing synthesis, we constrain the inputs/outputs of the design for certain input/output delays.How are scan inputs and scan outputs constrained? Appreciate any help.
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