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scan synthesis? What's your mean?
If you want a netlist with test ready state?
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i want test ready compile and inset scan chain. There are many gate-clocking in my design, when i run my script , there are many violation when dc execute "check_test" command, and it fails...
netlist sdf problems
Hi Han,
I have set_dont_touch attribute to "dem_clk" and "clk" "rst_n", "dem_clk" "clk" are the generated clock in my design , and "rst_n" is the generated reset signal in the design. I have look up the violation report that "clk" and "rst_n" are the high-fanout nets...
sdfnl1
Hi, all.
I have some probem in pre-simulation. When i simulate the gate-netlist with no sdf information, the waveform is OK, but when i simulate the gate-netlist with sdf annotation, the clock signal wave is wrong ( for example, dem_clk is one of clock signal in my design ,and it's...
but when "din" reach the cell slower than "en“ or when din is "x" state sometimes , the dynamic simulation indicate that dout will always be in "x" state.
search output design compiler
there is such a code in my design, but when i synthesize the code, i find the result is wrong. What's the problem? is it the problem of my code or it's a bug of DC? the target library is slow/CSM25.
the code:
always @ ( posedge clk or negedge rst_n)
if(!rst_n)...
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