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Re: Current Mirrors
Well, I am not sure this reasoning makes sense. The above equation just tells BJT gm is naturally much larger than CMOS gm. (gm=deltaI/deltaV)
there must be a physical explanation.
Current Mirrors
Hmm, there seems to a lot of reasoning but still hard to tell which one is better. As far as I heard, BJT is much better in terms of matching. One question here, does CMOS have poor matching in subthreshold? if so, any reason?
PLL simulation
Use HSIM. Define all digital circuits as digital and define analog circuits such as loop filter as analog, then it will be at least 100 times faster than spice simulation.
The unity gain bandwidth is Gm.effective/C. Thus, if you increase the gain by increasing Gm, then the BW will increase as well (assuming C remains the same). The phase margin is only depending on the second pole location and the unity gain bw assuming second pole is outside the unity gain bw.
PLL input clock
Try to use HSIM. Define analog block such as loop filter as analog and others as digital, then it will be at least 100 times faster than spice.
Re: LDO stability
If this is the case, the maximum value of Co should be limited for stability. Just for reference, the simple miller compensation is rarely used for LDOs since the LDO driver size is much bigger compared to 2-stage OA (so the gate capacitance of LDO driver is).
For the second...
ldo stability without esr
fanrong, these days many LDO parts use ceramic capacitor which has almost zero ESR. In this case, LDO stability can be achieved by making one pole dominant either at output or not. In your case since Co must be greater than a certain value, the dominant pole must be...
gm constant
nxing, I agree with you about feedback polarity. But, I don't quite understand how this can be stable.
would you please explain how (a) works even with positive feedback?
To me, it looks like LDO. So T12 is the power mosfet. But, the configuration is wrong as everyone mentioned (positive feedback). T14 needs to be cascode configuration to support higher Vi than Vdd. Otherwise, T14 will be stressed.
Definitely, Dummies!
The connection is right. If the drains are not tied together, it is very difficult to use dummy devices later on. It's not for matching! Who cares about the matching for inverter? Definitely not for ESD, either. ESD only for PADs and it doesn't look like good ESD, either.
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