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Recent content by Jinkyu

  1. J

    What's purpose of resistor to Error Amplifier's input?

    Thanks It really helpful! Maybe the designer wanted to set a certain Bandwith with reducing gain.
  2. J

    What's purpose of resistor to Error Amplifier's input?

    Thanks~. FvM Are you saying 'source degeneration'? Then I understand. But I don't understand that someone used pmos r2r amp(2'nd pic) as BGR. It doesn't need to lessen gain.
  3. J

    What's purpose of resistor to Error Amplifier's input?

    Hi! Let me explain for resistor to error Amplifier's input stage? Is it for noise? Thanks!!
  4. J

    [SOLVED] PSRR Inverter(logic) agaist input

    Thanks. sara_k_82 Startup circuit doesn’t work for normal operation. Startup’s input is connect to BGR’s output. So, PSRR is depredated because of parasitic Cgs in startup circuit. Noise is coupled with Cgs.
  5. J

    How to prevent gate oxide over stress on LDO pass element?

    What is the breakdown voltage of gate oxide and drain-source?
  6. J

    damage after metal fusing

    Have you ever experience damage after fusing. Fusing condition is 300mA for 6mS. The damage shows as vno and psrr in terms of AC characteristic. Do you have any idea for fusing circuit to prohibit damage?
  7. J

    [SOLVED] PSRR Inverter(logic) agaist input

    This is with and without LPF.
  8. J

    [SOLVED] PSRR Inverter(logic) agaist input

    Thanks for response. It's not psrr for VDD vs inverter's output. It's for VDD vs VIN. ---------- Post added at 03:52 ---------- Previous post was at 03:49 ---------- Acutually, I use startup(logic) to sense BGR voltage. It causes PSRR degradation. So I add LPF to reject power supply noise.
  9. J

    [SOLVED] PSRR Inverter(logic) agaist input

    Hello~ do you happend to know about PSRR for logic inverter input stage? Power supply noise reflect to input of inverter with -1.4dB. Plz, someone explain why. someone says that because of source follow, but I don't think so. Thanks
  10. J

    How to get "gm" of a nmos using spectre?

    ADE Results -> Print -> DC Operating Points
  11. J

    SpectreS simulator in Cadence

    matchinggroup= in spectre simulator use EXCEL with simulated data.
  12. J

    verilog, verilog-A and verilog-AMS

    verilog ==> log language such as c++ Verilog-A Verilog-AMS ==> describes analoge behavior such as resistor,cap,inductor or opamp
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