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No.You set an ideal current source (infinite impedance),so DC op. point won't be affected.
AC magnitude=1 and run small signal (AC) analysis.This is what i mean!
Inject an AC current source with magnitude=1 at your output,ground the input signal and finally measure the output voltage.
You have the output impedance!
Notice that in the whole procedure you should ensure to keep the correct DC operating point in both input and output terminals!
Alternatively...
Please upload the schematic and the respective layout while indicating the problem on the images.
Also show the properties (hit q) for this device at the schematic and layout.
You should open the ADE L/XL/GXL application and then run all the desired analyses from there.
You can google for this issue and search over the internet,there are lots of tutorial step-by-step for this kind of analyses,how to set them,run them erc...
After small-signal analyses (AC analyses)...
What about this (my latter suggestion) :
One question...have you tried with ASSURA instead of Calibre software?IBM from my experience recommends ASSURA for their PDK.Ignore this if your documentation recommends Calibre.
sxcut label sub! in your layout is not properly defined if i remember well...it should be defined with the drawing layer (drw/dg from LSW/palette) if i remember well.
You must study your pdk documentation to see what is the proper substrate methodology.This is confidential stuff i can't give...
At the schematic focus on the subc component.The down-terminal of this device should have a net attached on it and respectively named as sub!
Start from this and LVS again!
Note : I recommend not to use globals for the supply rails (vdd! & gnd!).Choose another name like VDD,VSS/GND that is not...
Dear forum members and experts,
I have some questions regarding the measurement of my taped-out active 3rd order butterworth filter.I am trying to extract the bode diagram of the filter.
I attach a screenshot that contains the schematic of the board (PCB) where the filter is placed.
The...
I am not aware of this technique...Could you explain further or give some reference to study?
If you do this,this is exactly the meaning,so your saying is valid.
I would straightly connect the SUB pin of the PAD to the substrate network via a wire named sub! (global) or whatever name you...
Ofcourse not!!But why you connect the bulk of the MOS to VEE (ground) via a resistor??
It depends on the substrate connection method that your PDK employs.Read the respective manuals/documents.
I think if you read your PDK manual you will solve the DRC errors and finally you must find a way to connect the nwell with Metal1 (try to find the correct name for nwell contact in your PDK manual or via the LSW window of Cadence,maybe
silterra gives a different name for this type of contact).
Almost yes...but you should place some (at least 2) nwell contacts in order to connect the nwell with vdd! with metal1.
More specifically,extend the nwell layer outside of the resistor's perimeter and put 2 nwell contacts in there,finally draw a metal 1 path from the contacts to vdd!
You should also connect the nwell layer to vdd metal in your layout.Did you do that?
The third terminal of the device in your schematic represents the substrate or nwell connection based on where (sub or well) the device is manufactured.
At the schematic side you have connected the middle terminal of the resistor's symbol in gnd! .Connect it to vdd! instead,since as you say this type of resistor is implemented in nwell and then LVS again.
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