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Hi Kevinrose,
if you want analysis power after PR, the best tool to use is Redhawk, this tool bases on spice information to perform power analysis, this is much more better than EPS.
if you just want to analysis power @ netlist level, I think primepower will meet you requirments.
I think you are a student, these kind of software is not free. I can tell where to download it. but the key point is that you don't know chinese. if yes, you can download it from here
https://bbs.eetop.cn/
Hi Nantha,
first of all, you need to check the clock skew in scan mode, if skew is ok, then you need to check whether this violation is true or not, ex: scan path should end at scan in pin of a flop.
if both of them are ok, you need to check the location density, if density is ok, fixing...
1. how do you get your dynamic ir results? I believe that you use vcd file to perform analysis.
2. how do you get your static ir results? I believe that you use a user defined toggle ratio to perform analysis.
compare 1 with 2, I believe you have got your answer.
%dc_shell> check_design
to check there are any unresolved module, if yes. check your search_path
you need to add Memroy Verilog top module(only input & output port information) to you Design
1. using library compiler convert lib file to db file
2. add the db file to your dc synthesis scripts, like "set link_library [concat $link_library $your_mem.db]
done !
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