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recently , i'm testing a sar adc . an arbitray wave generater or an active crystal as the clk signal of the adc in the test board.
and foud the dynamic performance of adc using active crystal better than that using the former one.
so how to improve the test results by using the AWG .?(50...
comparator of SAR ADC
hi,
i designed a comparator for SAR ADC. the AC simualtion results at a or b
port for ac input is shown below. something pullzed me.
1) for 1k or below , the gain is not enough , so does it mean the ADC can not deal with the <=1K sin signal.
2) the ac...
process porting
in my porting , for example smic18-->smic13,
in Scematic editing window: edit->search->replace (master mode porting).
after porting : a 4X inverter , the Multiplicity in CDF shows 1 but in netlist generated by ADE is 4 ( 4 is correct) , why the cdf is not updated...
as we all know, the dac output is just the input of comparator. my ref volt is 0~2.5V,so the mid-volt is 1.25V. 1. For example ,the 1st sampling point is 1.4 (p input) and 1.1 (n input), 0.3V differential, so the initial input of comparator should be 1.1(p input of comp) and 1.4 (n input of...
add a ramp signal as the source signal.
waht's the relation between the freq of ramp and the freq. of sampling? i means what freq of ramp is suitable for testing the static performance .
and what about the freq of sin wave for testing the dynamic performance, what's the coherent freq?
r2r calculate
Is the equation below all right or are there any some mistakes?
From the pic, current flowing the feedback res is If
And the vout=vcm+If*R can we get: vout in the pic
and the digital input code is sequenced from 0000 0000 to 1111 1111,and what’s the output of the dac ...
when i start spectre simulation, the it often shows "Greated directory input .ahdlcmi(770),compiling ahdtcmi modeule library'in the beginning of the output log file. what is really mean of the sentence in my simulation ?
i want to design a 8 bits SAR ADC, and i have designed one by weighted capacitor. i would like to decrease the power and area. i think i should choose the R-C weighted ADC whose msb is realized by cap for small area by using less caps. but i don't know how to decide the related bits, 5(cap)...
1. the Vgs1 is about 200mv,Vbs1=Vgs1=Vds1,so the bulk is forword biased. Vds1<0.7V. i also want to make the voltage as low as possible,but it is hard to make m3 m4 works in saturation region and m1 m2 in the sub-threshold region! M1,2,3,4 & Rb have certain relationship, but it's hard to find...
m1 2 2 6 2 nch w=? l=?
r 6 0 ?k
in this situation , how can i get the ibs(bulk to source) less than 200p(campared to Id whose value is about 200nA or some other proper value(nA)) (t=373k). m1 is woking in the subthreshold region with TSMC.25 process & the voltage at node 2 is about 400mV.
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