Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.
Can anybody share your experience about difference between simulation and measurement results? For example an LC-VCO's output frequency and phase noise. Which foundry's PDK is better?
Thanks.
Normally foundry will provide the gds mapping file. If no, you can also create the file based on Vituoso technology file and Astro technology file. You can find some infomation about the mapping file in Astro data preparation manual.
I think the reason is that the draw width not always the silicon width. When you tapeout your design, foundry will generate the lithography mask based on your layout firstly. But normmaly mask is different from your layout especially when OPC techonlogy is used to achieve better yield in 013u or...
Re: metal density error
About the qustion, it will be helpful to read some topic about Chemical–mechanical planarization(polishing) (CMP).
CMP is manufacture process.
I think floating dummy induce less capacitance.
I have tried to simulate a three parallel metal lines structure by Raphael. In the
structure three metal lines are named A, B and C from left to right. When metal B
is set to floating, the total capacitance on A and C became smaller.
Anyway...
Re: MOS parasitics
These parameters depend on your layout. It is hard to define a equation only by Width and Length. Normally the parameters are extracted from layout by LVS. BSIM model have default valuses for these parameters.
how to inteface calibre in icfb
My way:
Add the following two lines in the ~/.cdsinit file:
load "/mentor/ss5_cal_2005.2_6.10/shared/pkgs/icv.ss5/tools/queryskl/calibre.skl"
load "/mentor/ss5_cal_2005.2_6.10/shared/pkgs/icv.ss5/tools/queryskl/mgc_calibre_menu.skl"
Also the enironment...
Another way use Cshell command :
########################
#! /bin/csh -f
foreach cell (`cat lists`)
ps2pdf $cell
end
########################
File "lists" is the list of all ps files which can be created by unix command "ls *.ps >lists".
PDK = Process Design Kit.
It is circuit design environment. Normally PDK is created by foundry, which included all design-releted information of one process such as: simulation model, Pcell(parameters cell : defined by design rule), DRC/LVS/RCX technology files. Schematic-driven-layout and...
6t sram schematic
Thanks.
Can you also introduce me something about SRAM' Static Noise Margin(SNM)?I want to know how to write Hspice input file to calculate SRAM's SNM.
This site uses cookies to help personalise content, tailor your experience and to keep you logged in if you register.
By continuing to use this site, you are consenting to our use of cookies.
