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Yes I made the gnds and vias. But regarding the wires, those wires are to perform the measurements. And in that part is already DC not RF. Besides the wires are "relaxed" in the pic, while doing the measurements they are stretched below. But do you think that they still have an impact?
Thank you for the answer, it is indeed a RF rectifier. I considered the properties of the textile substrate, however, not sure if the ADS considers the substrate like a rigid PCB. Moreover, about the conductive ink, I only considered the conductivity and thickness, but are you saying that I...
Hi everyone, I have a question regarding my rectifier circuit. I performed it in ADS software, and there I obtained an efficiency of ~30%. However, when producing the rectifier, I measured it and instead of the ~30% I obtained ~0.5% efficiency.
The rectifier is on a textile substrate and the...
Hi everyone!
I'm desining some circuit, and I'm having this error after the layout:
"ERROR: (stdcmds.ael line 135, column 12)
Error generating netlist for "rectifiercircuit_lib:cell_23:myschematic": Failed to create netlist:
There is no corresponding terminal for `P2_POS connected by...
Yes, it was indeed one port that wasn't defined correctly.
Well I'm having now eff of ~0.3% and vout ~145 mV
I want to perform now the optimization, because in the schematic I had ~800 mV and wanted, if possible to achieve a similar output or at least half of it. And ocr increase de eff.... But...
Well, I rewrite them and here is the result:
The same is happening...
And what is the vout, you are obtaining? Because my vout from the schematic is ~800 mV and here ~3.6E-5 V.
Hi eveyone.
I finished the layout, and now I was simulating the schematic from the layout. And the results are really different, from the schematic, which I had efficiency of 30%, and now for the final results the efficiency is basically 0. Moreover, the output is also pretty bad compared with...
I did that, but now I'm having huge difference between the results in the schematic and the results over the layout. From the schematic I had efficiency of 30%, and now the efficiency is basically 0. Moreover, the output is also pretty bad compared with the schematic. Is this normal?
I believe...
Oh got it!
But, I tried now using order 1, to consider only the fundamental freq. and still can't perform the tuning, it claims that I need to simulate the cell first, which I did...
Error detected by hpeesofsim during HB analysis 'HB1'. Fatal error occurred while evaluating model...
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