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oh !! got it .. thanks ..
would like to summarize this:
- if amount by which delay scales down from worst corner to fast corner is not same for data and clock paths, and if data path scales down lesser than clock path, we may see setup violation under best corner ... here is an example...
@lostinxlation
in ur example also setup violation (3 ns) is more in worst corner only NOT in best corner ..
what interests me more is scenerio asked by agrey, is it possible to violate setup at best case (fast corner) and vice versa (violate hold at worstcase, slow corner) ???
i would suggest to design Intel's 8255, 8237 etc designs .. those are the very basic but includes all complexities one wishes to have ... also, those are protocols you must have studied already, u need not read protocol docs as well ..
all the best ..
can u post ur RTL code???
without looking at ur code, i can tell onething: ur design has timing loop (feedback loop) and so, DC has broken this timing loop by disabling specific path (timing arc)...
if these paths are clock domain crossing paths (defined as false path in functional mode), lock-up latch takes core of hold violation in test mode and synchronizers takes care of hold violations in functional mode .. what are others path which are false in functional mode and valid in test...
if you read command description for optimize_register command, it clearly tells that in presence of set_max_delay (and some more commands) retiming will be limited and infct sometimes it may worsen the timing .. reason behind this restriction also seems quite logical to me ..
u do one thing...
you will have to make tristate bbuffer transparent when in DFT mode .. same like your internal reset and clock .. try that and see if coverage is increased .. also it depends how many tri states you have and where exactl they are seating in chip ..
see, if functional path is valid, why will anyone define it as a false path?? and if it functional path is valid, hold and setup violation will anyhow be taken care .. is it not?
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