Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

Recent content by jaxshai

  1. J

    Hold time pass on FF, but failed on TT?

    Thanks for sharing your experience and it helps. BR Jax
  2. J

    Hold time pass on FF, but failed on TT?

    Thanks, avi. I agree your description above. However, for project timing sign off condition. Is it necessary to take Typical corner as one sign off condition, if the foundry just recommend to do worst/best, worst LT/best HT as sign off condition?
  3. J

    Hold time pass on FF, but failed on TT?

    Is it possible to pass the hold time check on Best Corner, but failed on Typical corner? Any one can help me out? Thank in advanced Jax
  4. J

    Explanation of .lib, .lef, .DEF, .tf formats

    Re: format It helps. Thank you!
  5. J

    Scoreboard and Checker in Testbench?

    Not sure. I only define Checkers and Monitors
  6. J

    Any method to make schematic transfer to verilog netlist??

    xwcwx, i know how to export cdl netlist. but how to transfer cdl netlist to verilog netlist ? any tools available? Thanks Jaxshai
  7. J

    Any method to make schematic transfer to verilog netlist??

    we have schematic , but now we want to implement it using SE . So , could we transfer schematic in cds5.0 to verilog netlist . so that we can use foundry's library to PR our product. Please help , thanks a lot!
  8. J

    Any method to make schematic transfer to verilog netlist??

    Under cds 5.033. I need a synthesizable verilog netlist in APR flow? Any advise? cheers jaxshai
  9. J

    Could GCF be supported by Enconter and Astro, other than SE?

    If cadence really do so, there must be some reason . But since there are littile different between GCF and SDC, i think it is not bad to learn GCF in SE first. Thanks kctang.
  10. J

    Are il and ile file relative with SKILL?

    il could be read as ASCII text file. But ile could NOT.
  11. J

    What files do I need to run SE ?(the same as in Apollo?)

    SE or Apollo I now find the constraint file format is not same for SE and Astro. SE is using GCF which was created by cadence few years ago. Astro may use SDC for its own constraint format. sigh~! I begin to feel that i could not keep the pace of the developing of EDA tools! So , system...
  12. J

    Could GCF be supported by Enconter and Astro, other than SE?

    Roger, Kctang. But ,is there any compatiblity between GCF and SDC? And i have noticed that SDC is the timing constraints from synopsys design compiler. If it is true, that means cadence will use synopsys constraint file format in its product : Encounter?
  13. J

    Could GCF be supported by Enconter and Astro, other than SE?

    ^@^ Please ! Cheers Jaxshai
  14. J

    Why is that IO pads operate at higher voltage than core?

    I think it is depended on your applications. Most foundry could provide different I/O for customers. such as 3.3/3.3 and 3.3/5.0.
  15. J

    Problem with configuring divided clock that uses flip-flop in CTS

    create_generate_clock Hi!! arunragavan, You will be appreciated for the CTS tutorials .^_^ Cheers Jaxshai
See more

Part and Inventory Search

Back
Top