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Hi folks,
I am an international student and graduate from Carnegie Mellon last December.
I am looking for ASIC related job, such as digital engineer, hardware designer or DFT designer. If you have opening in your companies or from friends', please leave your message or mail me...
Hi Folks,
In practice, we used register file, sram, dram as our storage devices for implementation of memory hierarchy. The capacity and performance (memory access speed ) is always a trade off.
I were asked a question. "why not use SRAM to build L1, L2 and L3? SRAM is faster than DRAM, maybe...
You could think this question in easier way :
DFF are formed by two cascaded latches.
The first one latch is negative-level sensitive.
The second one is positive -level sensitive.
In addition, where does setup-time and hold-time come from?
For setup time, it is the amount for capturing value...
Oh yeah ~ for tmp variable, it need 3 bits, => [2:0] tmp
Beside this, Is there any bug ?
I remember we should better separate combinational and sequential part in our design. It could save more gate counts for us?
So, in practice, style 2 is better them style 1? correct?
Thank you
Hi Folks,
I will like to design a counter (from 0~4)
and only for odd state (counter=1,3), output = 1. otherwise =0
This module gets two input clk and rst
I wrote two different code for it.
Which one is better? Thank you so much
counter 01234 01234
output 01010 01010...
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