Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Recent content by jasonkee111

  1. J

    Why Verilog $fread Only Read til 1658 Byte?

    Hi i am sure that my binary file is more than 2kB. It is fine when i am using fscanf using the same method but the data stored in normat .txt. Anyway, i am using mentor questa and i have file an service request to them.
  2. J

    Why Verilog $fread Only Read til 1658 Byte?

    I face an issue of $fread only read up to 1658 Byte. The snippet of code is below: byte TempDataBY[2000]; FileID = $fopen(BinFile.rbf, "r"); if (FileID == NULL) $error ("Error Open File: %s", FileName); while (!$feof(FileID)) begin ReadStatus =...
  3. J

    Grouping Modelsim Library

    Hi I have couple of library to be mapped. When i try to use the vsim -L library1 -library2 ... It is cumbersome. I thinking to group all the library into 1. So, i can use vsim -L All_Library. However, i have no idea on how to do it. Is there any better way? Pls advice. Thanks
  4. J

    PCIe Design Problem (BAR and Addressing)

    Hi I have a design which consists of 1 PCIe. PCIe communicates with the other component like onchip memory (slave) via BAR. PCIe Design http://i48.tinypic.com/n71krl.jpg As you can see, PCIe BAR 0 connects to CRA(control register of PCIe) and Onchip Memory. I have tried my design on the my...
  5. J

    How to tolerate the different clock ppm

    What is the different between in different clock inside the design and receiving a signal from another chip, which is driven by another clock? How can insert or remove symbol help to eliminate the ppm difference? i am trying to design a simple high speed serial interface which enables the...
  6. J

    How to tolerate the different clock ppm

    Are you sure that there is no way to compensate the different ppm? It is because i came across the rate matcher in the altera transceiver is able to compensate the different ppm.
  7. J

    How to tolerate the different clock ppm

    Hi Can someone explain on how to compensate the different clock ppm(different crystal) in a design? Is there any recommended article? Thanks
  8. J

    Understanding some concepts of CRC

    Hi. I have some question regarding CRC. 1. Shift operation is performed first and then the XOR operation or vice versa? 2. What is the difference between CRC 16 and CRC 32? How does this reduce the probability of failure? 3. Is Cascading of four set of CRC 8bit is equivalent to one CRC...
  9. J

    What is Train of PLL?

    Hi. Can someone to explain to me what is the meaning of train a pll? Any article recommendation? Thanks
  10. J

    verilog testbench: what is the purpose of ";"

    hi. What is the different between if (...) and if (...);? When to use it? Thanks
  11. J

    How to save specific signal in Modelsim

    I plan to running a simulation using verilog written testbench in Modelsim. I would like to save specific signal(s) into a file(any format). What is the syntax? Pls provide with some example. Thanks
  12. J

    what is meant by virtual clock definition and why do i need

    Re: asic virtual clocks i am a bit confusing here. Question: 1. The clock you mean is the clock send from other chip or oscillator? 2. Does the clock go through the general purpose IO or dedicated IO pin? 3. If the clock from other chip feed into IO, we don't need to use virtual clock?
  13. J

    Explain me concept of virtual clock in constraining design

    Re: virtual clock I am not really understanding on it. Can you provide some diagram and explanation. Your effort is much appreciated. thanks
  14. J

    confuse on the output properties of LFSR

    Ouput of LFSR Properties that confuse me: 1. "Ones and zeroes occur in 'runs'. The output stream 0110100, for example consists of five runs of lengths 1,2,1,1,2, in order. In one period of a maximal LFSR, 2n − 1 runs occur (for example, a six bit LFSR will have 32 runs). Exactly 1/2 of these...

Part and Inventory Search

Back
Top