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Recent content by jason_tian

  1. J

    how to design a trainning sequence forDFE?

    Hi all, I'm designing a DFE for GMSK, I found the training sequence could affect the training very much. So, I wonder if there's some theory of designing such a sequence? thanks!
  2. J

    how to choose a CRC algorigm, the Polynomial?

    how to choose crc Hi, when the order of a Polynomial is decided,how to choose further? for example, CRC-16 is different polynomialed in USB and X25,why?
  3. J

    How to do timing recovery with GMSK

    thanks!
  4. J

    How to do timing recovery with GMSK

    if you have some paper please upload here,thanks!
  5. J

    Problem with clk jitters in a 1/4 divider

    Re: devider jitters Hi, the jitter is got rid of as I removed the shunt cap to make the rise/fall edge sharp. thanks again!
  6. J

    Problem with clk jitters in a 1/4 divider

    devider jitters yes, maybe the rise/fall edges are too slow,for I shunt a 220p cap! thanks a lot echo47! I'll check it later and report the result.
  7. J

    Problem with clk jitters in a 1/4 divider

    Re: devider jitters Hi echo47, thanks! It's really a signal integrity problem! I disabled my oscillator of 'osc' and feed in with a SG,then, all things go all right. my oscillator is made of CMOS invertors. the wave is smooth on the oscilligraph(BW=200M,SR=1G) because I used...
  8. J

    Problem with clk jitters in a 1/4 divider

    Re: devider jitters Hi echo47, I checked the waveform of 'osc' in nanoseconds but found it's smooth. then I added another test signal 'tclk' as: ..... reg[2:1] devider; always @(posedge osc) begin tclk<=~tclk; if(devider>=2) begin clk<=~clk;devider<=1;end//osc/bclk=40k/5k=8. else...
  9. J

    Problem with clk jitters in a 1/4 divider

    devider jitters Hi echo47, thanks! I'll check the 'osc' signal. and do you think there a signal integrity problem within the CPLD due to bad decoupling of power supply?
  10. J

    Problem with clk jitters in a 1/4 divider

    devider jitters simulation in Q2 is ok, why the practical waveform varies?
  11. J

    Problem with clk jitters in a 1/4 divider

    Hi,everyone I'd like to make a 1/4 devider ('osc'/40KHz---->'clk'/10KHz) by the code as follows: reg[9:1] devider; always @(posedge osc) if(devider>=2) begin clk<=~clk;devider<=1;end else devider<=devider+1; the waveform of 'clk' jitters, sometimes the 'clk' raises or falls on a...
  12. J

    Error: Node "modD" of type Logic cell has no legal

    of type register cell has no legal location I've resolved,pinplanner caused
  13. J

    Error: Node "modD" of type Logic cell has no legal

    of type logic cell has no legal location Hi,pls have a look at my code below: ......... reg modD,txFlag; inout mod; .......... ......... assign mod=txFlag?modD:1'bz;//tri_state. ....... ---------------------------- I code as above in Q2,but the fitter says:'Error: Node "modD" of type Logic...
  14. J

    FSK modulation of 1Mbps data on a PLL loop

    the frequency deviation is subject to the bandwidth and BER you want to achieve, plz refer to some communication books for such a diagram.
  15. J

    How to phase shift the frequency to 90 degree at 418 Mhz?

    Re: phase shift you can also take PLL into account if you need a precise phaseshift.
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