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Hi, In my opinion the best description of the basic theory of sigma-delta pll's is found in the book "Delta-Sigma Data Converters".
By reading this book it is easier to grap the concept of the sigma-delta method and see how it relates to a fractional pll realization.
It is by the way found here...
cadence vs mentor vs synopsys
Funny you say so Sergio, I would absolutely prefer IC Station for Layout. This is all due to the 'strokes'. It is a couple of years ago that I used Cadence, but I guess Cadence still haven´t got strokes.
When you first know all the strokes you can work extremely...
users.cybercity.dk/~bse1977/phd
Yes there are books e.g CMOS FRACTIONAL-N SYNTHESIZERS by Bram de Muer and M. Steyaert. This is pretty much the Phd thesis from DeMuer.
Personnally I was not that crazy about Stichelbout's thesis. I much preferred Perrotts (https://www-mtl.mit.edu/~perrott/)...
Well this partly depends on what loop gain you want. The larger current you use the larger capacitors needed for the loop filter. So if you intend to integrate the loop filter on the chip go for small currents. But often larger currents are better for suppressing noise and spurs (well the larger...
Re: question about FIB
Focused Ion Beam (FIB) is a method where you can deposit new metal and/or remove/cut existing metal traces on a fabricated IC. This is done as the name implies by a Focused Ion Beam.
To be able to use the technique you first have to etch a hole in the package and...
Re: LC's VCO
Hi
Here you have some more;
The first one contains a short intro, and ends with a design guide:
https://www.ee.columbia.edu/~kinget/papers_files/aacd99_book.pdf
The rest are theses, some old some new, but as you will see they are pretty much following the same guidelines...
drc for anntena
Regarding your second question; Yes, the etching of long metal lines accumulate large charges on the metal, and when it has no discharge path it might break down the gate oxide.
So if you intend to use a long metal1 line connected to the gate then this will accumulate charges...
No, Don't redesign!
The 'donut' is just a trick to make the layout extractor think that the grounds are separate!
So (as mentioned) the actual physical ic will have a common substrate (bulk), and therefore a direct connection will exist between the two different grounds (through the psub...
Re: RF ic test
Production Testing of Rf and System-On-A-Chip Devices for Wireless Communications (Artech House Microwave Library)
An Introduction to Mixed-Signal Ic Test and Measurement
lmx2326 wont lock
I guess you typed a wrong frequency range in the post? Or are you trying to use a vco ranging from 1805-1880MHz to reach a minimum frequency of 1970MHz?? If so I can understand why the tuning voltage is 5volt!.
Your problem could pretty well be answered in this (recent) thread;
So is the output not pulsed, but the PLL is in lock ?(and the tuning voltage is between gnd and vcc) if so I guess you don´t have a problem but if it is still not in a locked condition try some of the following;
Check the frequency out of the Reference divider and the Prescaler (as stated...
Re: Delta-Sigma Synthesizers
This is probably not of any help (so maybe i shouldn't post it..) But If you look in a book like Norsworthy´s "Delta-Sigma Data Converters". You will see that even higher order SD-modulators are tonal near the integer (ref harmonics) and all commercial SDMs on the...
In generel the old paper from Razavi is still a good introduction to the topic; "Design Considerations for Direct Conversion Receivers", which can be found here; **broken link removed**.
As mentioned you can do a lot in the digital domain, but if your baseband chain exhibits just a recent gain...
Re: Fabrication
What do you mean ?, are the pex-tools extracting to few/many parasitics or is it the circuit models you are talking about ?
Please tell more details...
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