Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.
jtag controller +vhdl
The protel99se pcb & sch are pretty good!
But the problem is the ACT8990 not easy to get.Can anybody use FPGA or CPLD to replace this chip???
plx write main configuration registers
The LCLK is 25MHz,I do assert Ready_n after ADS_n,but I use address to differenciate the 2 peripherals(FPGA's registers and ADV611).FPGA's internal registers doesn't have ACK_n,ADV611 has its ACK_n.
I wonder PLX's functions is the only way to configure...
how to access the pci9054 using fpga
Thanks for ur replay! :D
U may misunderstand that I said the intervals of continous read or write cycle is 12us,rather than the singal read or write cycle itself . The singal cycle is quite fast it consumes 4~5 LCLK,I wonder what the OP system do when in...
pci9054
In my project I use PCI9054 "C Mode" to control FPGA and other peripherals.Acturally PCI9054 acts as local bus master and PCI target.
I successfully realize the signal cycle 32 bits read & write.But it quite slow,the interval between two continous read or write is more than 12 us.To...
pci 9054 interface to fpga
In my project I use PCI9054 "C Mode" to control FPGA and other peripherals.Acturally PCI9054 acts as local bus master and PCI target.
I successfully realize the signal cycle 32 bits read & write.But it quite slow,the interval between two continous read or write is...
altera usb blaster driver download
kawk's last modification was pretty good.
I think a power on reset is needed in the statemachine,then statemachine can goto default state waiting commands from usb.
Thanks for yasser_shoukry & nand_gates 's help.
To yasser_shoukry, I prefer your coding styles.Just like u said toggle all signal in the combinational process,and if u want the signal to be registed u can use dff in the sequential process.
To nand_gates,when I assert WR_n or RD_n ,I will...
First of all ,thanks for your replay.:D
This time I post my code here.I want to use PCI9054 to control my FPGA and other peripherals.So I have to convert PCI9054 synchronous signals to asynchronous signals ,just like wr_n,rd_n,ack_n and etc.
The problem is the code sometime behaves good...
I wrote a state machine something like this:
--
process(clk,rst_n)
begin
if rst_n = '0' then
current_state <= s0;
elsif clk'event and clk = '1' then
current_state <= next_state;
-- toggle some bit according to state
...
end if;
end process...
This site uses cookies to help personalise content, tailor your experience and to keep you logged in if you register.
By continuing to use this site, you are consenting to our use of cookies.
