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Recent content by jalinmes

  1. J

    Is the calculation of the conduction loss on charge pump correct?

    U didnt answer the question. This paper is assuming there is a loss on it and it is calculating how much the loss is. Verifying the way they calculated it is what I was asking
  2. J

    Is the calculation of the conduction loss on charge pump correct?

    Shouldnt the conduction loss of the flying cap shown in the attached file equal to= Pc= (2Iout)^2 /(fc) In the paper it shows Iout^2 instead of (2Iout)^2 is the mistake by the paper or my understanding is wrong If what is shown in the paper is correct, then why? thanks,
  3. J

    output voltage output stage

    how to set the output operating point of the output stage at half vdd? if by the attached photo guidance in common mode condition, first stage can be folded before designing the second stage. as shown in the photo. the guidance is trying to make the current of M7 equal to M6 to make the...
  4. J

    Power emission mask calculation

    is the calculation this way correct. If by following table 8.1 at the link shown below, **broken link removed** (b)&(c) specs are taken into account because it is more relax. cdma baseband is 600KHz so RF band is 1.2MHz so based on the specs for 30KHz resolution, the specs will be -60 + 10...
  5. J

    CDMA FCC emission mask

    Did you see it at 3gpp website?
  6. J

    CDMA FCC emission mask

    I dont know how to find it from there actually. Iactually searched it before posting my question here
  7. J

    CDMA FCC emission mask

    Hi Does any one knows where to obtain cdma fcc power emission mask for handheld device? I need the one which shows ACPR offset more than 2MHz Thank you,
  8. J

    Waveform distortion at the output in a NMOS diff pair

    Re: diff pair distortion It doesnt exceed. The input voltage swing is big, amplitude is 400mV
  9. J

    Waveform distortion at the output in a NMOS diff pair

    diff pair distortion Hi A sine waveform being sent to a nmos diff pair. there is a nmos current source at the bottom and the load is a pair of pmos diode connected. If the dc voltage level at the input is 3 volt, i got the distorted waveform at the output as shown in the photo. However the...
  10. J

    DC Power Consumption vs PAE

    If I want to compare [1] & [2] still can i normalize [1] output delivered load to be the same as [2] and then compare the power consumption? 2.32/6 = x /22 , x=8.506 so [1] consume less power than [2]? compared to 13 or they actually cannot be compared regardless the frequency difference or...
  11. J

    DC Power Consumption vs PAE

    DC power consumption & PAE Hi What is the best way to measure the duration of the circuit? Let's assume there is no PAE vs Power consumption curve plot to see. If people want to evaluate a duration of a circuit, can they only look at PAE without checking power consumption? or they need to...
  12. J

    DC power consumption & PAE

    Hi What is the best way to measure the duration of the circuit? Let's assume there is no PAE vs Power consumption curve plot to see. If people want to evaluate a duration of a circuit, can they only look at PAE without checking power consumption? or they need to look at both? or they look at...
  13. J

    off grid error drc error

    Fortunately the updated design has been submitted it again ontime, thank you.
  14. J

    off grid error drc error

    Hi I found there is one off grid error in the file i submitted yesterday. Can some one pls tell me what will happen to it? They said the project is released for run and ask me to resubmit it asap. I want to know what if i miss it, what will do with this off grid problem? This trace wont be...
  15. J

    Post-layout simulation problem

    setting gmin = 0 , didnt work. I changed the parameters to as follow. It worked. Do you know how accurate this can be if I run by tran conservative but set iabstol to 1uA. And where can I find the definition of those parameters? such as vabstol, gmin, iabstol, pivrel, reltol, etc. Thank you. it...

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