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Recent content by jakejake

  1. J

    does synopsys dft_drc simulate SE=1?

    Hi, my question is: does synopsys dft compiler simulate SE=1 when performing dft_drc? When doing dft drc debugging, I see SE=X in design vision. Is this supposed to happen? Thanks.
  2. J

    Basic question about EDT

    bypass will help you do diagnosis.
  3. J

    DFT & Synthesis: Scan clock inversion and non-unate warning

    Some experienced ppl do use DFF to generate scan mode signal, so that scan mode signal's transition can be at speed.
  4. J

    magma talus dft scan insertion problem

    Anyone knows how to specify the module name for buf/inv used in scan insertion by Talus?
  5. J

    Scan chain insertion concepts , ATPG and boundary scan/JTAG in DFT

    Re: DFT help I think you should get a book like "digital systems testing and testable design"
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