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Recent content by Ivan_Ryger

  1. I

    VIVADO: crossing clock domain - poor placement message

    Klaus, I don't have the code right by hand, but you are right. We don't start numbering from 1 but from zero. Then the frequency should be halved.
  2. I

    VIVADO: crossing clock domain - poor placement message

    Klaus, the clock at 26th tap should be 125MHz/2^26 what is roughly 1.9Hz. The counter updates every clock strike, so transmitting the 16 digits data through parallel interface to the FIFO is at 1.9Hz and not every 16 seconds. The second side of the FIFO can run at much higher speed. Please find...
  3. I

    VIVADO: crossing clock domain - poor placement message

    Dear Klaus, 1. I need only a SPI master controller to feed the MAX7219 7 segment driver with serial data. 2. My master clock frequency is 125 MHz and is connected to the pin L16 - feeding directly the programmable logic of Zynq XC7Z010. 3. The BCD counter is four decade-wide (16 bits). Possibly...
  4. I

    VIVADO: crossing clock domain - poor placement message

    Yes, you are right, this was a typo. Instead of checking the logical value of clk I planned to check the logical value of the divider. reg [26:0] divider; always @(posedge clk) divider <= divider + 1; always @(posedge clk) if (&(divider)) clk_slow <= 1'b1; else...
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    VIVADO: crossing clock domain - poor placement message

    Dear Barry, I am using the standard constraint file for Zybo development board, so I haven't modified the master clock input. Anyways, it seems that with enabling the clock for only one strike helped to solve the issue with the compiler. I check if the counter has maxed up (by doing logical...
  6. I

    problem with connecting usb to intel 80c51

    The 80C51 does not have enough computing power to process enough instructions to decode the USB protocol. Better way is to use FT232 chips externally and take the benefits of already implemented RS232 interface in the controller.
  7. I

    VIVADO: crossing clock domain - poor placement message

    Dear colleagues, I am trying to design a small BCD counter that outputs its value via SPI interface. The speed of the BCD counter is not critical, it reads an incremental sensor. The faster part of my design is the SPI interface that runs at a couple tens of kHz. After studying the concepts...
  8. I

    Transistor or LED as Varicap?

    Varicaps are, somehow, less noisy as the avalanche region is quite far away from their standard operation region. You may probably use the transistor BE junction. It can be an interesting experiment to prove it, but I would advise to use some common varicaps in the final solution. Mainly for the...
  9. I

    Transistor or LED as Varicap?

    Dear ZlatkoMM, the varactors based on NPN transistor have usually low Q when the C-B junction is used (due to high series resistance). On the other hand, this junction has usually high Miller capacitance, what is desirable for varactor operation. Therefore, the C-B junction capacitance change is...
  10. I

    SPICE radio frequency amplifier design and optimization

    Dear all. Recently I have started designing a radio frequency amplifier based on dual-gate MOSFET BF998. I have simulated it in HSPICE simulation software, designed input and output matching networks. Unfortunately, This is a four-parameter problem which is suitable to be solved by optimization...
  11. I

    Parallel RLC equivalent circuit for Microstrip Antenna

    I found something here...
  12. I

    Schematic of Laser Projector/Beamer design

    Good morning, I am actually dealing with the laser projector from elm-chan.org I have built the controller board, designed new printed circuit board, but after assembly and loading data into MMC card, the controller displays "no item" even if there are files(*.txt , *.frm) in MMC card. have you...
  13. I

    MW oscillator with interdigital filter

    The exact frequency is determined by two conditions, the amplitude and the phase one. The interdigital filter has the central finger connected to ground via varicap. This diode tunes the center frequency of IDT filter and also affects the phase of transmission coefficient. The IDT filter is very...
  14. I

    MW oscillator with interdigital filter

    Today I have tested the performance of new IDT filter fabricated on 0.8mm FR4. It has 0.5mm spacing between fingers. The measured peak resonance insertion loss is about -10dB @2.15GHz and -13dB@1.75GHz. It seems that the colophone resin has increased the insertion loss. This PCB is without...
  15. I

    MW oscillator with interdigital filter

    I will try to measure the distances between interdigits. If I remember well, it was 1mm (PCB fabricated from picture on that website). Maybe this is an issue. Another reason is the dielectric loss of FR4. I will try to measure it. I used BFP420 transistor. Now i wait for BFP182 as long as the...
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