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Re: clock uncertainity
Sometimes clock skew is helpful to us . It decreaes the time period of the clock and increases the frequency, as i the case of positive skew .
frequency decrease skew
Positive skew is sometimes helpful to us
It decreases the minimum clock period and increases the max clock frequency of operation
Re: about inverter
To get equal rise time and fall time, size the nmos and pmos inverters in the opposite ratio of their mobilities. (W/L)n/(W/L)p = (mobility)p / (mobility)n
In AnalogVLSI , low power design is the key now a days ..Also mixed signal design as u place the digital and analog circuitry on the same chip ..there will be probs like clock transmission, interconnect delay etc....
Re: fets as resistance
THere are 2 regions of operation in FET, one is the saturation where current remains virtually constant of vds ...... In the other region caled the triode or the linear region , the current increases linearly with Vds but the slope will increase with Vds ...... This means...
Re: VHDL==> Verilog (want to learn verilog, presently use
Hi dude
Actually , if u knwo VHDL , u can learn Verilog but thru a bit struggle .....Forget the coding part....Except the syntax..they would be the same almost...
But one thing what I had observed is that , it is difficult to synthesize...
verilog synthesis free
a simple tool is provided in Samir Palnitkars' CD..When u buy that book, he gives u a demo tool..Else u can try out FPGA Advantage tool ..U can get it free fom any cracked site
Re: Begin - End
Begin End statements do not cause any extra hardware burden....
U can check this after writing a small verilog code and synthesizing it ...... There wont be any extra gates in the synthesized circuit due to this Begin-End statements
SImon Haykin is best
Also refer John G Prokais
If u are a starter and you dont knwo anything,, first read BPLathi and only then u go for these
U can also refer Bernard C Sklar
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