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Recent content by ithink

  1. I

    PLL cricuit with ADF4106 Problem [hlp]

    PLL Problem [hlp] if improve pn in band, pls decrease loop BW,But too small may cause noise worse! so pls design divider,CP and vco more carefully!
  2. I

    how to use hand calculation to solove jitter after pll done?

    jitter calculation + pll how to use hand calculation to solove jitter after pll designed, please tell me! thanks
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    What is stability or Right-Half-Plane

    stability is very important to close loop system,such as op amp,pll. there are a lot of methods to solove, such as root locus,bode plot. but they are different, u have to select one that you like. if you don't know what i said, please refer to book <<signal and system>> and read s domain...
  4. I

    Calculate noise figure using Hspice

    please refer to hspice help document, which introduces noise analysis.
  5. I

    Question:how to change 8-phase signal to 16-phase signal?

    hi,i have used delay circuit to get the function,but this method may be not stable, someone have better methods? could you offer to me?
  6. I

    Ring oscillator stages (N)

    ring oscillator prime number i think there is no relation between stages and form of ring oscillator. maybe diff oscillator is more common in circuit design.everyone know frequency of vco decrease with increase of stages.ring oscillator stages? it's up to your need!
  7. I

    Question:how to change 8-phase signal to 16-phase signal?

    NOW i try to use phase interpolator to implement conversion of phase, maybe you have some advice to me about phase interpolator,thanks
  8. I

    Question:how to change 8-phase signal to 16-phase signal?

    hi, i have designed a pll with 8-phase clocks, now i need 16-phase clocks, how to change the 8-phase clock into 16-phase clock? my msn:atlantic_lin@hotmail.com thanks
  9. I

    very low current comparator please help

    here i have a little advice to you about power consumption. u can add more switch transistor, when the circuit works, all swich is open; however ,when the circuit don't work, all the switch is closed,then all the circuit will have lower power.i have designed a rtc chip,which has 1ua power.
  10. I

    CLOCK AND DATA RECOVERY?

    simulink phase shift thank you, analogartist the final aim is to design cdr circuit satisfied our require, i just start from math model, and step by step to circuit design. now i don't understand phase interpolater in cdr system, i have been designed pll circuit sucessfully,but cdr differs...
  11. I

    CLOCK AND DATA RECOVERY?

    clock and data recovery book hi,everyone i am suffering great difficulty in my research about CDR design,i have read some papers, such as ''a 10gb/s cmos cdr circuit with an analog phase interpolater'' ,and so on, and made a lot of effort to learning cdr principle.but i have no progress in...
  12. I

    What is the most important concern on PLL design?

    stability is more important performance than other characteristics in pll design, even as SkyHigh said,phase noise is not the most important but always an issue, noise lie in every module,such as vco,lpf. here paper PLL_sutra.pdf may offer some advice, u can google it on internet
  13. I

    how to evaluate and calcualte jitter in designing pll?

    hi,I have designed a several MHz pll and calculated some parameters,such as lock time, damp factor;but i don't know how to evaluate jitter? for a pll, jitter is very important parameter and determines the pll is good or not. i wil appreciate your help! thanks
  14. I

    several questions about pll's stability and verification?

    hi, i have been designed a 48M pll,but i have no idea to verify its stability and correct. At the beginning of design, in order to attain 48M output frequency, we made some suppose,such as phase margin Φ=50°,loop bandwidth ω=20k,and so on; we design 2nd loop filter according these suppose and...
  15. I

    comparator circuit design?

    hi,sunking i have designed the comparator that i need according to the rail to rail op. thanks best wish! ithink
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