Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

Recent content by ishan.dalal

  1. I

    [SOLVED] Substitute for records structures of VHDL in Verilog

    Hi Dave, I need to use verilog since it's the requirement of the project. Is there any way I can parameterize the code in verilog? VHDL has packages, records which helps in parameterizing the code. How to do the same thing in verilog?
  2. I

    [SOLVED] Substitute for records structures of VHDL in Verilog

    Hi, I am working on converting a VHDL code which is heavy on records structures usage to verilog. It's a highly parameterized code using packages. I am also new to Verilog. Is there any substitute for records in verilog?
  3. I

    Divide by N counter where N is odd integer

    Hi Guys, I understood divide by 3 counter. I was wondering if there's a generalized method to implement Divide By N counter where N is ODD like 5, 7, 9 and so on. Thanks in advance:smile:
  4. I

    Understanding divide by 3 counter waveforms

    Got it, Thanks a ton !
  5. I

    Understanding divide by 3 counter waveforms

    Hey I understand that. The thing I am unable to understand is the timing in waveforms. How Q1 and Q0 produce one clock pulse every 3 clock pulses?
  6. I

    Understanding divide by 3 counter waveforms

    Hi, I have uploaded two images. One is counter design and second is waveform. I am unable to understand how Q1 and Q0 produce one clock pulse for every three clock pulses.
  7. I

    Understanding divide by 3 counter waveforms

    Hey Guys, I am not able to grasp the waveforms of divide by 3 counter where two flip-flops produce waveforms at half frequency but at quadrature phase relation. Could anyone please explain me waveforms? Thanks in advance !
  8. I

    How to double clock frequency using XOR gates?

    Please show with waveforms if possible
  9. I

    queries related to CMOS design

    1) How does the size of PMOS Pull Up transistors (for bit & bit- lines) affect SRAM's performance? 2) What's the critical path in a SRAM? 3) In a SRAM layout, which metal layers would you prefer for Word Lines and Bit Lines? Why? 4) For an AND-OR implementation of a two input Mux, how do you...
  10. I

    What's the critical path in SRAM?

    I came across one of the answers of this question in one of the threads. "Critical path in the SRAM is activated when a logic 1 is read from the cell at the first row's last column. This constitutes the critical path because when the word line is asserted from the row decoder, it has to charge...
See more

Part and Inventory Search

Back
Top