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Recent content by Ironlord

  1. I

    [SOLVED] CRC Calculator in VHDL.

    I have developed the following code to calculate a CRC. I am passing it a Start signal and a Frame, which is 12-bits of data. The CRC works picking up the message in Nibbles, so as I have 12-bits, I will divide it into 3 Nibbles. I am trying to simulate this code on ModelSim, but when I put the...
  2. I

    Fitter Error (14566): Cannot place 1 periphery component(s) due to conflicts with 1 fractional PLL

    The problem is I am not using a baseline file, I created a new project from zero. I can do other kinf of staff with the FPGA, but the LVDS communication is being imposible to do. My FMC connector only has pins on the banks 4A and 8A. Whenever I assign one of those pins to the LVDS_TX it fails...
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    Fitter Error (14566): Cannot place 1 periphery component(s) due to conflicts with 1 fractional PLL

    Update: I have made a new project. The HPS was deleted, my idea now was to use an external clock. To do so, I thought using another FPGA, generate a 50Mhz clock and connect it to an input pin. Well, the design has been implemented, and I added the PLL (to convert the 50Mhz input clock into...
  4. I

    Fitter Error (14566): Cannot place 1 periphery component(s) due to conflicts with 1 fractional PLL

    I have tried to debug my problem. 1.- I created a new project and introduced the HPS to obtain a clock signal. 2.- The first test consists on blinking some leds with the clock signal and a counter. I also outputed the clock to see the signal on the oscilloscope. It works perfect. 3.- I added...
  5. I

    Fitter Error (14566): Cannot place 1 periphery component(s) due to conflicts with 1 fractional PLL

    Thanks for your advice. I'm following your steps and will try to make it fit. Just in case, how could I delete the region constraint you mention? I mean, how can I tell to Quartus where do I want to place the PLL? My work on VHDL has always fitted without any problems. This is the first time...
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    Fitter Error (14566): Cannot place 1 periphery component(s) due to conflicts with 1 fractional PLL

    First of all, thank you for your responses and your help. I really appreciate it. I tried. Those warnings of unasigned pins is because the board does not have a clock, so I have to create a QSys system and pick the clock signal from the HPS. I have runned the TCL scripts, but I can't give those...
  7. I

    Fitter Error (14566): Cannot place 1 periphery component(s) due to conflicts with 1 fractional PLL

    Hello dpaul. Thanks for your response. I'm not sure if I have done it right, because is the first time I found this kind of error, but I have tried to apply the proposed solution. I runned the following Tcl Commands from the TCL console: set_location_assignment PIN_H15 -to rxClockIn...
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    Fitter Error (14566): Cannot place 1 periphery component(s) due to conflicts with 1 fractional PLL

    Hello mates! I am trying to do a LVDS communication for testing purposes before the real project. The aim is to communicate via LVDS with a high-speed ADC @ 800mbps. On my test, I have used a Terasic DE10-Nano development board (which does not accomplish with the desired voltages) and it went...
  9. I

    How to use a termination resistor?

    Then how do I reduce the overshoot. I am going to work with other drivers and I shouldn't let my FPGA give more than 3.3V or it may reduce the board's life. The peaks are of 4.5-4.7V in average. I wanted to make different comprobations, so I was thinking in a test with a 25 Ohm and another one...
  10. I

    How to use a termination resistor?

    I want to add a termnation resistor to reduce the overshoot of a signal. I configured in Quartus to be 25 Ohm resistance, but it gives me back an error. It says it is not posible to use with 3.3VTTL/LVCMOS. In case you are wondering, I am generating a SPWM. There are a total of 7 outputs from...
  11. I

    [SOLVED] Quartus and fixed point

    I have finished compilling it and it works!!! I added the fixed_pkg.vhd, fixed_float_types.vhd and txt_util.vhd. The sources seemed to be different. I had the file "fixed_pkg_c.vhd" which was long and another one from another source wich was "fixed_pkg.vhd" and was quite shorter. I had to...
  12. I

    [SOLVED] Quartus and fixed point

    Ok, I ordered the files from Settings->Files Both, "fixed_float_types" and "fixed_pkg_c" are on top. I have tried the two combinations and the result is in both cases the same. The error still the same I posted in the first picture.
  13. I

    [SOLVED] Quartus and fixed point

    Hope this help. I think I am doing what you are posting, but it doesn't seem to work.
  14. I

    [SOLVED] Quartus and fixed point

    Could you give me some more details. I have also readen this other answer from you in another thread: https://www.edaboard.com/showthread.php?373860-Compile-package-into-quot-ieee_proposed-quot I have added the file to the project, changed the properties to "Library File" and it doesn't work...
  15. I

    [SOLVED] Quartus and fixed point

    Well, I'm using Quartus Lite. I tried to import the library adding the VHD files to the project and referencing them on the place where I use the ufixed data type. It still throwing error with 93 and 2008 compilers. What am I missing or doing wrong? I didn't understand you, but it sounds good...
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