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Recent content by irisaru

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    Problem in calculation inductance from Sp simulation - ADS

    Dear Volker, Thank you very much for your help. Your app notes are very helpful. Best Regards, irisaru
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    Problem in calculation inductance from Sp simulation - ADS

    Dear all, I am simulating the inductance and coupling coefficient of transformer using ADS. My procedure consists of three steps. First, I create a transformer using CoilSys in ADS and then simulate its S-parameter, then I separate this transformer into two inductors and simulate their...
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    [SOLVED] Problem with creating a transformer using CoilSys - ADS 2017

    It is millimeter and when I change it to micrometer, the Coilsys works well. Thank you very much for your help
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    [SOLVED] Problem with creating a transformer using CoilSys - ADS 2017

    Hi all, I have a problem when create a transformer using CoilSys addon in ADS 2017. My transformer has W = 3um, S= 3um, the outer dimension are 200um, the primary and secondary turn are 3. I have setup the length unit in ADS in micrometer, and the substrate is defined in micrometer too...
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    (VerilogA) How to plot two different output transition follow input condition

    Hi all, I want to plot two output transition follow the input condition in verilogA. Here is my code if (V(in[7]) == 0) V(vout) <+ transition ( vout1, trise, tfall); else V(vout) <+ transition ( vout2, trise, tfall); However, the compiler reported that " Do not use the 'transition'...
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    Problem in design 3bit idea DAC to decode signed binary to decimal

    Hi all, I design 3bit idea DAC using verilogA to decode the signed binary to decimal. My purpose is change: 100 -> 4 011 -> 3 010 -> 2 001 -> 1 000 -> 0 111 -> -1 110 -> -2 101 -> -1 I used modelwriter tools in Cadence Spectre to design DAC with parameter (max voltage = 4; min voltage = -3...
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    Help with simulate sigma-delta modulator

    Hi kappa_am, I also design Sigma delta modulator (SDM) MASH 1-1-1 for fractional-n pll in Cadence, Could you please give me some advices in simulate SDM power spectral density? Because SDM MASH 1-1-1 has 3 bits output and I do not know how to simulate its psd, Thank you, Irisaru
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    Design of Double down conversion of superhyterodyne receiver

    Thank you for your opinion, I totally agree with you on IF of 22.5 MHz giving easier filters and reduce image frequency rejection. But my project is RF tuner design so I need a demodulator to decode the IF signal. The commercial product of demodulator IF input are usually 36/44 MHz, some of them...
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    Design of Double down conversion of superhyterodyne receiver

    Hi, For the frequency range 54MHz - 860 MHz, I have found that some papers use " Up/Down Conversion Architecture", the first IF is usually 1.2 GHz, and the second IF is 36/44 MHz. Could you please tell me why the call the 36/44 MHz is the standard IF? Thanks
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    X band power amplifier transistor (9 - 11 GHz)

    Hi everybody, I want to design a power amplifier with Pin maximum is 17dbm and the Pout is 33dbm for X band ( 9-11Ghz ) in Roger substrate. I want to use a power transistor with package, not in a die. Do you have any suggestion for me ? I have found X-band transistor, FLM0910-3F...
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    Microstrip Transmission Line ADS

    I think you can find these equations in microwave books, for example Microwave Engineering, David Pozar
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