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how to simulate an nmos varactor in accumulation mode in cadence?how to check to mode of operation?is any inbuily symbol available for it or we have to simulate it using nmos transistor only?
please help me out with the working of capacitor bank..
i am using capacitor bank that involves the use of an inverter separating two nmos varactors..i don't know how it works..??
the frequency should be 20 GHz and the differential opamp should be stable and should have less error.
as frequency is inversely proportional to the open loop gain and directly proportional to error
i want that the cmos differentil opamp should have a higher open loop gain that is required for an ideal opamp.But at higher frequeny, open loop gain decreases. so how to work t higher frequencies such that gain is constt. and high?
ideal opamp circuit in gyrator circuit in differential configuration is to be designed in cadence tool. So what parameters should be taken care of and what should be done to make this opamp as an ideal one?
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