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colpitts oscillator simulation in ads
Dear All,
I'm simulating with a conventional Colpitts oscillator in Cadence. As the SpectreRF User Guide suggests, to initialize the oscillation, it should require some initial conditions on L or C, or some brief impulsive stimulus into oscillatory node...
qpss plot
Hi,
I have a question related to Monte Carlo simulation for a mixer IP2 in Cadence using QPSS+QPAC.
For a single point simulation, I can have the IIP2/OIP2 result from "Direct Plot -> qpac -> IPN Curves"
after setting a few parameters. I don't know how to set up the corresponding...
layer purpose pair
At the CIW window (the initial window),
1. go to File->Import->Stream;
2. load .gds file at "Input File";
3. specify the target library name at "Library Name";
4. ready to go!
Thanks, oermens. It works perfectly for both single iteration and Monte Carlo simulation! In my version of AWD calculator, the exact menu for " Memories->Select" is "Recall" though.
In case some people need to know the detail, after recalling the variable from calculator memory, at the Analog...
Thanks a lot, oermens!
I try to load the variables into AWD calculator at CIW command line,
but the list was empty when I checked "var" button in the calculator.
I guess I may miss something from your tips.
Best Regards,
Y. Jin
Dear All,
I'm currently doing an inductor Monte Carlo simulation in Cadence-Spectre (Cadence version: 5.10.41_USR5.90.69; Spectre version: 6.2.0.420). My objective is to see how the inductance and Q-factor (differential-driven) changes over process variations.
I set up a few expressions to...
Re: single nmos lvs
Hi,
It turned out that for the designkit I'm currently using, the 'pintext' (instead of 'pin') layer should be used for the pin definition. After the changes, the lvs is clean.
Cheers,
Ian Jin
Re: single nmos lvs
Thanks for the tip. Unfortunately, currently I'm working with an immature designkit, no extraction tool available yet. Any other way to look around this problem?
An interesting observation is that, once I put this transistor in a higher-level circuit (e.g., a cascode...
single nmos lvs
Dear All,
I'm currently working on a single transistor layout. The transistor has four pins in the schematic (namely, gate, source, drain and bulk). In the layout, I define four pins accordingly, using 'pin' layer for both pins and labels. But after LVS, none of the pins are...
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