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Recent content by iamluqi

  1. I

    can this cmos circuit operate??

    The NMOS may not open even if high voltage. Also the bulk/substrate voltage may matter here. The topmost pmos may be reverse -biased
  2. I

    simulink implementation of the fft algorithm

    This is like a multi-rate discrete sim. User defined function (eg. s-func) may not easy to achieve this. U may consider using some implicit multi-rate conversion blocks already built in simulink(eg. p2s/s2p blocks).
  3. I

    how to reduce cell leakage power in large design

    reserve a separate supply rail for body. Generally std cell lib provides such an option
  4. I

    synthesized netlist as input for power

    multiple corner multiple mode analysis in PT should be a common feature now. Just refer to the manual on how to do it. If the foundry still wanna make money it would not make the gate types different between its different characterization corners.
  5. I

    set_input_transition in prime time

    find one in the tech lib and scale it down somewhat
  6. I

    They say static IR drop causes SI noise and delay.

    SI noise and delay are similar things caused by cross-talk through capacitor in layout. If IR drops some portion of the circuit slows down and which in turn increase the chance of overlapping timing windows between timing paths that are physically close to each other. Timing report may hen have...
  7. I

    Low power design : Active-Low or Active-High Reset ?

    From the flip-flop layout perspective, it may be smaller in size if zero reset since NAND is more effective than NOR.
  8. I

    Is there a way to constrain signal logic value in DC

    Theoretically there would be some win in gate count, isnt it?
  9. I

    Is there a way to constrain signal logic value in DC

    Say there is a bus signal A[1:0], and designer knows later after RTL coding that the valid value for signal A is 2'b00, 2'b01, 2'b10, but not 2'b11. Is there anyway to set this signal value constraint so that DC knows 2'b11 is dont-care input and help the logic optimization? I found DC cmds...
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