Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

Recent content by hys

  1. H

    Vlsi jobs for freshers..

    Re: freshers vlsi jobs in bangalore New batch of "Advanced Verification with System Verilog" is starting on 24th Dec 2011. Get in touch with us at info@vlsitraining.net **broken link removed**
  2. H

    please give me suggestions

    There is lot of demand for VERIFICATION engineers in VLSI domain... Getting a professional training in Verification + System Verilog will definitely increase your chances of getting into a VLSI industry by 100% ... We are starting a course soon.. and we focus on real challenges faced in industry...
  3. H

    M.Tech-VLSI freasher seeking for job

    Getting a professional training in the VLSI domain will surely increases your chances of getting into a VLSI industry. We are soon starting a course... VLSI Training (Design / Verification) Course starting in RajaRajeshwari Nagar, Bangalore. Check the Brochure @ **broken link removed** Course...
  4. H

    Job opportunities in INDIA for a ECE fresher

    VLSI Training (Design / Verification) Course starting in RajaRajeshwari Nagar, Bangalore. Check the Brochure @ **broken link removed** Course starting on 18th June 2011. Registrations are open.. Contact 9845752236 ASAP
  5. H

    Is there Openings for Embedded Freshers

    VLSI Training (Design / Verification) Course starting in RajaRajeshwari Nagar, Bangalore. Check the Brochure @ **broken link removed** Course starting on 18th June 2011. Registrations are open.. Trainers are from Industry... so you get to learn from their real-time experiences. You can talk to...
  6. H

    Looking for SpyGlass software and manual

    Re: Help me SpyGlass While purchasing, they offer some rule-sets specific to your requirements.... U gotto carefully choose the rule-sets that u need...
  7. H

    vlsi basic n verification related faq's

    Its a very open question.... If u just want some basic idea, best thing is to try google.. If u have anything in specific to be answered, post that here clearly... Best Regards, Harish https://hdlplanet.tripod.com
  8. H

    UART DESIGNING >>>I NEED HELP

    Bit Clk is much faster than the data you transmit. And in real time, there is a possibility of some unpredictable delays on the TX / RX lines... so the data might be shifted +vely or -vely by a few bit clks.... In order to counter this phenomenon it is usually a practice to sample the data at...
  9. H

    VCD file generation in VHDL

    It also depends on the simulator whether it supports VCD file dumps... In case of Mentor's modelsim, it has some commands like - vcd file - vcd add <signal_name> These commands can be used to get vcd dumps of the chosen signals.. Best Regards, Harish
  10. H

    Glitch detection in RTL using Spyglass/Conformal/Debussy

    Re: glitch detection This is a "Clock Domain Crossing" scenario... You can use Spyglass & its clock domain crossing rules or Mentor's 0-in CDC for analyzing such circuits... 0-in CDC does a very analysis... it has a whole lot of built in rules which are meant for clock domain crossing checks...
  11. H

    Advantages of writing testbenches in Verilog rather than in VHDL

    Re: Verilog testbenches Ajeetha, I agree with u that VHDL has more capabilities as compared to plain verilog. But if you consider the normal testbench requirements, in my experience I havent seen much difference. However I have been using VHDL since many yrs. Vera and System Verilog...
  12. H

    How to watch the memory content at any stage of simulation?

    Re: Watch Memory content You can use "Chipscope" from xilinx.... you need to determine before compilation what signal you want to be able to observe. Then you connect the memory signals to be observable. Then during runtime it is possible to observe them... You need to read through the...
  13. H

    Run Time FPGA verification

    You can definitely go for "Quickturn-Palladium"... This is not FPGA... but something similar... you can still be able to achieve your goals. I would rate it higher than FPGA verification. Debugging on quickturn is far more easier and it provides lot more features.. Best Regards, Harish...
  14. H

    The Verification Language trend is Systemverilog

    Yes.... any vendor is fine if you are starting now. But if you are already a user of Specman - e and trying to migrate to SV, then you better look at Synopsys as they have something more than SV itself... something called as "SV extensions" which can help u in migrating from e to SV. Best...
  15. H

    Writing testbench in verilog or e language?

    You could have read the earlier messages... u wud have got the answer... Anyway.... repeating again, VERA is going to be phased out sooner or later.... System verilog is better than that... You could even use specman - e which is equally powerful as a verification tool. Regards, Harish...
See more

Part and Inventory Search

Back
Top