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  1. H

    Impact of surrounding logic - causes

    Hi, https://i.imgur.com/vsNsjOh.png suppose that I have an FPGA, and, based on the image above, that I have a circuit that is synthesized on the bottom-left part of the FPGA (green box). Furthermore, suppose that I synthesized another circuit (red box) that surrounds the first. This last...
  2. H

    Clock quality's influence on setup's times

    Hi, I'm searching for some material (papers, slides, books' chapters, etc.) that talks about the influence that the clock's quality has on setup's times and other timing charateristics. I've tried to search online, but I've not found much. I'd be very grateful if you could give me some...
  3. H

    FSM: Moore or Mealy?

    Exactly! Thanks for the answers... I would add: could I consider that FSM as a Moore+Mealy (but described with one process)? Basically is Moore for certain outputs and Mealy for the other ones... Is this wrong?
  4. H

    FSM: Moore or Mealy?

    Hi, just a quick question... I have developed a FSM using VHDL and I'm questioning about if it is a Moore or a Mealy FSM. Here is the code: -- FSM states type state is (idle, init, init_shift, subtract, test, operation_sub1, operation_sub0, correction, finished); signal current_state...
  5. H

    Parallel stadium of Pipeline

    Hi, I have a Spartan-E3 FPGA and I'm realizing a (parallel) pipeline with 4 stages like this: https://i.imgur.com/6CQNk.png The two stages "T3" are the same. T1, T2 and T4 "run" at 50MHz, while T3 runs at 25MHz (and 180° shifted like in the figure). In Behavioral Simulation it works fine, the...
  6. H

    Maximum frequency on the board

    Yeah, I know it's very slow because I used a MAC multiplier (signed 16 bit) :( I can't use any other multipliers (especially the ones embedded in the FPGA that are VERY FAST), so I have to arrange like that :( The data path delay is 54.335ns <=> ~18MHz, but it's a "lie", because I need to run...
  7. H

    Maximum frequency on the board

    "my pipeline only works at 10 MHz" means that if I set the clock to 10MHz, it never fails to produce the result. "test my pipeline" means that I see the pipeline output on the 7-segments display. I don't know HOW I can figure out what I have to change :\ Any hint? By the way, if useful, this...
  8. H

    Maximum frequency on the board

    Hi, I realised the pipeline that I talked before (https://www.edaboard.com/threads/275809/), but now I have some doubts on the maximum frequency. I have a Spartan-3E FPGA running at 50MHz and I want to test my pipeline on it. I linked the output result with the 7-segments display and all works...
  9. H

    Pipeline - Multiplication problem

    Ok, thanks for the answer. I have another question: if I put my sequential multiplier into the second stage, is this correct? Or I should implement my pipeline INSIDE the FSM of the sequential multiplier? I don't know if I rightly explained myself ... sorry for the English ^^
  10. H

    Pipeline - Multiplication problem

    Hi :) I have to realize a pipeline to execute this expression: (A+B)^2 - C[D - (E/2)] A, B, C, D and E are all signed 16 bit. However I can divide that operation into three (or four) stages: 1°: x=A+B and y=D-(E/2) (the division delay can be negligible because it's a simple right shift) 2°...
  11. H

    Undesiderated 1-bit latch

    Thanks, you enlightned me ^_^ I rewritten my FSM and now it "works", except a warning that I receive in the Implementation phase. (Yes, because... nothing, at least seems so) Here is the incriminated part: https://pastebin.com/N53F6Fhz What am I doing wrong? That's the only warning I receive...
  12. H

    Undesiderated 1-bit latch

    Hi, I'm programming a N-bit non-restoring divider, but I faced a little problem. I have an Operative Part (combinatorial) and a Control Part (Finite State Machine). The Control Part has a 2 processes FSM, 1 for updating the next state and 1 for the "state sequence". update: process(clk_in...
  13. H

    Inconsistent Post-Route simulation (ISE)

    You are right. I tried with a 20ns clock constraint and this is the Post-PAR Timing Report:
  14. H

    Inconsistent Post-Route simulation (ISE)

    Shift, data_in, reset and enable are inputs. The only output is data_out. However you are right, thanks for the answer. I changed my test bench and now the inputs don't change at the same time of the rising edge of the clock. This is a simulation running with a 4ns clock period: It seems...
  15. H

    Inconsistent Post-Route simulation (ISE)

    Hi, I created an 8bit Barrel Shifter and now I want to simulate it using Xilinx ISE tools, specifically I want to do a Post-Route simulation (the last step). I do these steps: 1. Synthesize - XST 2. Implement Design 3. I check the "Synthesis Report" and find: "Minimum period: 3.281ns (Maximum...
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