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Recent content by hxnudt

  1. H

    question about VCS Save/Restart simulation with Denali MMAV model

    when I try to use VCS Save/Restart simulation feature in my design, the Denali MMAV model report some Error like this: *Denali* Error: Checkpoint, Save/Restart disabled. I think I have to add some code to Denali PLI routines, but I can't find the solution in the MMAV userguide, Could anybody...
  2. H

    Who's goin to dominate the nex-generation HDL world?

    i think it is SystemVerilog
  3. H

    My trouble in H.264 decoder design

    My trouble in H.264 decoder design I want to implement it in ARM+ASIC:slice header and above is going into SW,my ASIC finish MB header and below .Do you think it work?My trouble is how can i add testbench to my disgn,and is it necessarey to write systemc model, i want to write it in verilog...
  4. H

    when a Z input to DFF , what output of DFF?

    model is ok, in real circuit the output is 0 or 1 unless metastability
  5. H

    Do somebody build H264 decoder SoC use CEVA DSP?

    32bit dsp 64bit databus
  6. H

    Do somebody build H264 decoder SoC use CEVA DSP?

    Do somebody build H264 decoder SoC use CEVA DSP? now our project in trouble , the CEVA core’s datacache seems not use because the HSIZE on AMBA is SINGLE , and my colleague told me that it is caused by the bridge between the CEVA core’s 64bit bus and AMBA 32bit bus. I want to know the...
  7. H

    /Can somebody give me some advice about ESD simulation? /

    Can somebody give me some advice about ESD simulation? I want to use Hspice to simulate ESD,but i don't know how to make an equivalent circuit model of ESD,can somebody give me some advice to do this,and does my ideal wrong,any other EDA soft can I use?
  8. H

    //Can somebody give me some advice about ESD simulation?

    Can somebody give me some advice about ESD simulation? I want to use Hspice to simulate ESD,but i don't know how to make an equivalent circuit model of ESD,can somebody give me some advice to do this,and does my ideal wrong,any other EDA soft can I use?
  9. H

    Can somebody give me some advice about ESD simulation?

    Can somebody give me some advice about ESD simulation? I want to use Hspice to simulate ESD,but i don't know how to make an equivalent circuit model of ESD,can somebody give me some advice to do this,and does my ideal wrong,any other EDA soft can I use?
  10. H

    What is Electronic Design Interchange Format (EDIF)?

    Re: What is EDIF? what is the relation or difference between edif file and spice netlist(or cdl file ect.) I think all these netlist files only describe the connections of modules(or transistors) in your design,but it need some other files to descripe your modules .My question is how can the...
  11. H

    [SOLVED] How to minimize the delay in an inverter cascade?

    delay minimization the principle is "fanout 4",see more information in the recommended book digital integrated circuits JAN M.RABAEY Berkeley
  12. H

    [SOLVED] smallest no of transistors

    pass transistor logic may be the best way to reduce the number of transistor,but i think it is difficult,especially in complex logic
  13. H

    transceiver v.s. cascade inverter

    reduce delay time
  14. H

    what is source synchronous devices..??

    it sounds unimaginable! i can't understand either
  15. H

    Does cadence IC5 has windows version?

    Cadence support Linux or Solaris,no windows vesion because of its low efficiency!
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