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Recent content by hustwill

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    Calibre LVS error "Bad component subtype"

    I use Cadence composer draw a "BUF" schematic, and lead to the layout XL(virtuoso XL) BUF layout. But when I did the LVS check with Calibre, it report the errors: bad component subtype: layout: source MP(P18LL) MP(P18) I don't...
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    Simulation problems using veilog-a

    simulation problems I wrote a behavior model of VCO using verilog-a, then created the simbol. Then, I create a simulation schematic to simulate the VCO in Cadence composer. When I simulation with spectre, I don't know how to set the model libraries, so I just passed it. When I simulated, the...
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    Which EDA tool converts schematics to layout?

    eda tool Is this usful ? I think it is better to figure the layout by hand. And you'd better design your schematic hierachily.
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    Assura LVS problem for TSMC 0.18 MIXED SIGNAL process

    I think you should update(connections->update) your layout from your schematic first.
  5. H

    Skill : chamge PDK for differnet process

    If anyone know, please tell me too, I also need it.
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    Calibre mismatch problem.

    I think you should update the layout according to the schematic first.
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    Need Help on Designing Voltage controlled ring ocillator?

    I want to design a VCO. Three Step ring ocillator. The center frequency is 200MHz, the frequency domain is 0-400MHz. I have the circuit architecture,but how to determine the paramiters? Is there anything that I need to consider? I don't know what to do next.
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