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Re: Beginner's Questions
try this style:
process
variable Code_of_Operation : INTEGER range 0 to 2;
constant Variable_1 : INTEGER := 0;
begin
case Code_of_Operation is
when Variable_1 | Variable_1 + 1 =>
Operation := 0;
when Variable_1 + 2 =>
Operation := 1...
first, consider if delay is really needed. And consider again...
if delay falls into the domain of one of your applied clocks then choose ff, shift register or counter to implement the delay.
if you are not able to use clock, synthetizers can prevent objects from being optimized.
Eg...
found logic contention at time bus node
i am not expert with max, but i am sure it is not license matter.
actually, what is your problem with bidir.vhd?
by, husoo
ps.: your e-mail address does not work...
find logic contention
in first line, modify your testbench; you cannot read and write in the same time on the D bus, as i see. No busmaster does it so and now, your bench should behave like an MCU or whatever, i suppose.
hope the code below could be applied for your cpld.
entity cpld is
port(...
8051 logic contention
at 40ns your process is active thanks the sensitivity list for changing. d in (ff) will conflict d out(BufA).
although, the read part of the process does null, this only means d out keeps the previous state: BufA. (i think it is not the only one event during the course of...
Re: VHDL Problem
synopsis fpga express can except:
a small skeleton if you want a bidirectional bus/port:
entity fpga is
port(
...
bus : inout Std_Logic_Vector(n downto 0);
rd_neg: in Std_Logic;
...
);
end fpga;
architecture fpga_arch of fpga is
-- signals for the internal registers
busin...
rising_edge falling_edge
sorry, but y do u need to do so? u drive 2 different signals... u can put them into seperate processes as usual. Omitting the reset:
process1(Clk)
begin
if rising_edge(Clk) then
signal1<=...
end if;
end process;
process2(Clk)
begin
if falling_edge(Clk) then...
use them! :-)
i mean to say that you should get them connected into the state machine flow. for example, if the SM steps into one of the unwanted states, make a transition into the reset or even better a known state to signal this problem.
however, maybe..., better solution to code the states...
ram control vhdl
why do u use ram? what for? if the fpga is fast enough to read such a speed like ADC goes then why do u store temporarily samples in ram? just write in and read out. It doesnt make sense to me... or I dont see every detail?
by!
cpld clock multiplier
in cpld 95xx there is no resource to multiply frequency, so u should build up an asynchronous freq multiplier or change cpld to another type, use fpga with dll, change external freq, or ...
Anyway, with asynchronous circuit u can only double the main freq afaik.
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