Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.
Hi, Could you please give some examples of functional corners? I understand transistor PVTs are : SS, FF, SF, FS and TT. Interconnect corners: C-worst, RC-worst, C-best, RC-best.
temperature inversion is already accounted for in the question I believe, since they are saying pick up best and worst values for Temperature (two values).
What other will impact timing other than P,V,T? Is it parasitic corners that are missing, which makes number or corners go up? Or possibly...
What are the reasons behind running the signoff at so many corners in today's chips. Why we can't tapeout the chip with running a few worst corners? like pick up the best/worst for Process, voltage, and temperature each, and run signoff test at all possible combination of all these. (2 x 2 x 2)...
Related to Digital design Netlist to GDSII flow:
what happens if a timing constraint is defined on a cell output pin and the cell is deleted? Is the constraint lost? Should that cell have to be prevented from deletion by applying an attribute?
You may want to see what two layers are specified as your clock preferred layers (M3/M4 or M4/M5 or M5/M6), higher is better, that can help to some extent.
Regards,
Re: To keep ICG at high level of clock tree, any better way to fix "EN" setup violcat
Yes, two birds with one stone, make the tool aware of the clock skew at the Clockgate before CTS, this will drive ideal mode optimization to work harder ie. as much as it needs to, to meet timing.
Hope it...
Jeevan.life wrote:
optimizing for local skew only will not be able to meet the timing due to global skew. Take a broader picture, the flops maynot talk to each other but may be the logic can get merged at some point which will violate timing because of global skew.
--
Its not clear to me.
Lets...
Hi
Seems by definition:
local skew is the skew between any two flops that have a path between them
global skew on the other hand is the skew between any two flops on the same clock group even if they donot talk to each other.
Its seen that EDA tools work on optimizing global skew and not...
Are you adding the clock period in your calculation? The clock period is independent of the delay that needs to be added. 1500ps - 200ps = 1300ps needs to be added.
Regards,
The most important thing to ask the interviewer is - DOES THIS HOLD AND SETUP VIOLATION HAPPEN ON SAME PATH OR DIFFERENT PATHS? IT CHANGES YOUR ANSWER. If same path, clock frequency needs to be 11ns. If different, then first lets fix hold on that path such that it doesnot affect setup here which...
You say its a long net, assuming that you are in post routing stage, Its best to make least disturbance to the rest of the design.
- I suggest you highlight the net in layout, in whatever tool you are using.
- Estimate the total length of the net, and number of buffers you will need.
- Pick a...
This site uses cookies to help personalise content, tailor your experience and to keep you logged in if you register.
By continuing to use this site, you are consenting to our use of cookies.
