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Recent content by hsy54hsy

  1. H

    question about spectre ac analysis

    Thanks a lot for your advise, magic happens:smile:
  2. H

    question about spectre ac analysis

    ---------- Post added at 06:41 AM ---------- Previous post was at 06:41 AM ---------- [/COLOR]nothing there
  3. H

    question about spectre ac analysis

    Actually, I can run the simulation in the way you mentioned. BUt I am too lazy to do this and want to look for a more convenient way to do this:)
  4. H

    question about spectre ac analysis

    because the bit control signals of one block are generated by another block after some logic canculation
  5. H

    question about spectre ac analysis

    when running ac analysis, the defualt circuit stage is @0s how can I run the ac analysis using the DC bias condition @ other time, for example 200ns? waiting for your help thanks
  6. H

    How to add pins in the post layout netlist

    I have run the post layout simution with cadence. To simulate the loop stability, wo have to cut the node in the feedback loop for simulation. So I find the nodes in the netlist file, rename some of the nodes to sapseparate it into two nodes. Then I make the two nodes into pins by adding the...
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